From cc248bcce3ba0a1d9f392d1fcb8b55bac10ada98 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sun, 6 Sep 2015 16:01:33 +0800 Subject: [PATCH] mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clock BRANCH=none BUG=none TEST=test it ok on oak-rev3 Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350 Signed-off-by: Patrick Georgi Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4 Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5 Original-Signed-off-by: Chunfeng Yun Original-Reviewed-on: https://chromium-review.googlesource.com/297942 Original-Commit-Ready: Yidi Lin Original-Tested-by: Yidi Lin Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/13094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/mediatek/mt8173/include/soc/pll.h | 1 + src/soc/mediatek/mt8173/pll.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index aa9c8bbca9..1eab709462 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -284,5 +284,6 @@ enum { void mt_pll_post_init(void); void mt_pll_init(void); void mt_pll_set_aud_div(u32 rate); +void mt_pll_enable_ssusb_clk(void); #endif /* SOC_MEDIATEK_MT8173_PLL_H */ diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 4f386c0a32..3faf7859a7 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -443,6 +443,23 @@ void mt_pll_init(void) (1 << 4) | (1 << 2) | (1 << 0)); } +/* Turn on ADA_SSUSB_XTAL_CK 26MHz */ +void mt_pll_enable_ssusb_clk(void) +{ + /* set RG_LTECLKSQ_EN */ + setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1); + udelay(100); /* wait for PLL stable */ + + /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ + setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1); + setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1); + udelay(100); /* wait for PLL stable */ + + /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ + setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); +} + + /* after pmic_init */ void mt_pll_post_init(void) {