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soc/intel/broadwell: Drop reg-script usage from bootblock PCH init 

Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46352
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-13 20:33:35 +02:00
parent ec05de6f54
commit cc2708797e
1 changed files with 51 additions and 37 deletions
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88
src/soc/intel/broadwell/bootblock/pch.c
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@ -7,7 +7,6 @@
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/rcba.h> #include <soc/rcba.h>
#include <soc/spi.h> #include <soc/spi.h>
#include <reg_script.h>
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <southbridge/intel/common/early_spi.h> #include <southbridge/intel/common/early_spi.h>
@ -46,49 +45,64 @@ static void set_spi_speed(void)
SPIBAR8(SPIBAR_SSFC + 2) = ssfc; SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
} }
const struct reg_script pch_early_init_script[] = { static void pch_enable_bars(void)
/* Setup southbridge BARs */ {
REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), /* Set up southbridge BARs */
REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
/* Set COM1/COM2 decode range */ pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1);
REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
/* Enable legacy decode ranges */
REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
/* Enable IOAPIC */ pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN);
REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
/* Read back for posted write */
REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
/* Set HPET address and enable it */ pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
/* Read back for posted write */
REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
/* Enable HPET to start counter */
REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
/* Disable reset */ /* Enable GPIO functionality. */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN);
/* TCO timer halt */ }
REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
/* Enable upper 128 bytes of CMOS */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
/* Disable unused device (always) */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
REG_SCRIPT_END
};
static void pch_early_lpc(void) static void pch_early_lpc(void)
{ {
reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); pch_enable_bars();
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_config);
/* Enable IOAPIC */
RCBA16(OIC) = 0x0100;
/* Read back for posted write */
(void)RCBA16(OIC);
/* Set HPET address and enable it */
RCBA32_AND_OR(HPTC, ~3, 1 << 7);
/*
* Reading the register back guarantees that the write is
* done before we use the configured base address below.
*/
(void)RCBA32(HPTC);
/* Enable HPET to start counter */
setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0);
/* Disable reset */
RCBA32_OR(GCS, 1 << 5);
/* TCO timer halt */
u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT);
reg16 |= TCO_TMR_HLT;
outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT);
/* Enable upper 128 bytes of CMOS */
RCBA32_OR(RC, 1 << 2);
/* Disable unused device (always) */
RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
} }
void bootblock_early_southbridge_init(void) void bootblock_early_southbridge_init(void)