soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()
This change uses cpu_phys_address_size() to calculate the size of high MMIO region instead of a macro for each SoC. This ensures that the entire range above TOUUD that can be addressed by the CPU is used for MMIO above 4G boundary. Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
abd4714ee0
commit
cc35f723fd
|
@ -45,6 +45,4 @@
|
|||
#define EARLY_I2C_BASE_ADDRESS 0xfe020000
|
||||
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
|
||||
|
||||
#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
|
||||
|
|
|
@ -54,8 +54,6 @@
|
|||
|
||||
#define HECI1_BASE_ADDRESS 0xfeda2000
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
|
||||
|
||||
/* PTT registers */
|
||||
#define PTT_TXT_BASE_ADDRESS 0xfed30800
|
||||
#define PTT_PRESENT 0x00070000
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
@ -102,8 +103,8 @@ void sa_fill_gnvs(global_nvs_t *gnvs)
|
|||
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
|
||||
|
||||
sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
|
||||
gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
|
||||
printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n",
|
||||
gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb;
|
||||
printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n",
|
||||
gnvs->a4gb, gnvs->a4gs);
|
||||
}
|
||||
|
||||
|
|
|
@ -48,8 +48,6 @@
|
|||
#define VTD_BASE_ADDRESS 0xFED90000
|
||||
#define VTD_BASE_SIZE 0x00004000
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
|
||||
|
||||
/*
|
||||
* I/O port address space
|
||||
*/
|
||||
|
|
|
@ -70,8 +70,6 @@
|
|||
#define VTD_BASE_ADDRESS 0xfed90000
|
||||
#define VTD_BASE_SIZE 0x00004000
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
|
||||
|
||||
#define MCH_BASE_ADDRESS 0xfea80000
|
||||
#define MCH_BASE_SIZE 0x8000
|
||||
|
||||
|
|
|
@ -61,8 +61,6 @@
|
|||
#define PTT_TXT_BASE_ADDRESS 0xfed30800
|
||||
#define PTT_PRESENT 0x00070000
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB)
|
||||
|
||||
/*
|
||||
* I/O port address space
|
||||
*/
|
||||
|
|
|
@ -76,9 +76,6 @@
|
|||
#define VTD_BASE_ADDRESS 0xfed90000
|
||||
#define VTD_BASE_SIZE 0x00004000
|
||||
|
||||
#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
|
||||
|
||||
|
||||
#define MCH_BASE_ADDRESS 0xfedc0000
|
||||
#define MCH_BASE_SIZE 0x20000
|
||||
|
||||
|
|
Loading…
Reference in New Issue