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mb/google/sarien/variants/sarien: Set up tcc offset for sarien 

Change tcc offset from 15 to 3 for sarien.

BUG=b:122636962
TEST=Match the result from TAT UI

Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Su 2019-01-10 21:52:39 +08:00 committed by Duncan Laurie
parent c3e75b42a4
commit cc394d4d37
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@ -74,6 +74,9 @@ chip soc/intel/cannonlake
#| I2C1 | Touchpad | #| I2C1 | Touchpad |
#| I2C4 | H1 TPM | #| I2C4 | H1 TPM |
#+-------------------+---------------------------+ #+-------------------+---------------------------+
register "tcc_offset" = "3"
register "common_soc_config" = "{ register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = { .i2c[0] = {