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Add support for FID/VID changes messages. 

Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will
assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how
long. Imho for 100us. Which is more than plenty (2us required) I will try
to justify this once I know what bios to set in SB.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2007-11-13 15:40:21 +00:00 committed by Uwe Hermann
parent 3adc30eed5
commit cc3ccdb643
2 changed files with 11 additions and 0 deletions
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4
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
View File

@ -309,6 +309,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif #endif
init_timer(); init_timer();
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
enable_fid_change();
init_fidvid_bsp(bsp_apicid);
needs_reset = optimize_link_coherent_ht(); needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);

7
src/southbridge/via/vt8237r/vt8237r_lpc.c
View File

@ -222,6 +222,13 @@ void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */ /* SCI is generated for RTC/pwrBtn/slpBtn. */
outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
/* FIXME: Intel needs more bit set for C2/C3. */
/* Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
} }
static void vt8237r_init(struct device *dev) static void vt8237r_init(struct device *dev)