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mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB 

This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB.

Changes for chromeos.fmd:

SI_BIOS:
    RW_SECTION_A/B: Increase to 7.5MB.
    RW_LEGACY: Introduce with 1MB.
    RW_MISC: Increased to 1MB.
    RW_UNUSED: 2MB (reserved)
    WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2023-04-06 19:53:49 +05:30
parent 589f6b9c04
commit cc4ca5ec94
1 changed files with 24 additions and 16 deletions
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40
src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd
View File

@ -4,39 +4,47 @@ FLASH 32M {
SI_ME
}
SI_BIOS 23M {
RW_SECTION_A 7604K {
RW_SECTION_A 7680K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 4400K
}
RW_MISC 152K {
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 7604K {
RW_SECTION_B 7680K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 4400K
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
# It is placed in the common `chromeos.fmd` file because it is only 4K and there
# is free space in the RW_MISC region that cannot be easily reclaimed because
# the RW_SECTION_B must start on the 16M boundary.
RW_SPD_CACHE(PRESERVE) 4K
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 8M {
WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_GSCVD 8K
RO_SECTION {
FMAP 2K
RO_FRID 64