diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index a735c04db5..0f24f71c9f 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -33,6 +33,7 @@ void tco_disable(void);
 void punit_init(void);
 int early_spi_read_wpsr(u8 *sr);
 void mainboard_fill_spd_data(struct pei_data *pei_data);
+void set_max_freq(void);
 
 /* romstage_common.c functions */
 void program_base_addresses(void);
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 00710fe837..87b1af09df 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -181,6 +181,7 @@ void soc_pre_console_init(void)
 void soc_romstage_init(struct romstage_params *params)
 {
 	/* Continue chipset initialization */
+	set_max_freq();
 	spi_init();
 
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index e1095b2f09..42e624cab9 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -103,12 +103,6 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
 	/* Get power state */
 	params.power_state = fill_power_state();
 
-	/* Print useful platform information */
-	report_platform_info();
-
-	/* Set CPU frequency to maximum */
-	set_max_freq();
-
 	/* Perform SOC specific initialization. */
 	soc_romstage_init(&params);
 
@@ -435,12 +429,6 @@ __attribute__((weak)) void report_memory_config(void)
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
-/* Display the platform configuration */
-__attribute__((weak)) void report_platform_info(void)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
 /* Choose top of stack and setup MTRRs */
 __attribute__((weak)) void *setup_stack_and_mtrrs(void)
 {
@@ -449,12 +437,6 @@ __attribute__((weak)) void *setup_stack_and_mtrrs(void)
 	return NULL;
 }
 
-/* Speed up the CPU to the maximum frequency */
-__attribute__((weak)) void set_max_freq(void)
-{
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
 /* SOC initialization after RAM is enabled */
 __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
 {
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index c0c7a7b70d..ac1d6a0d38 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -88,12 +88,10 @@ void mainboard_add_dimm_info(struct romstage_params *params,
 			     int channel, int dimm, int index);
 void raminit(struct romstage_params *params);
 void report_memory_config(void);
-void report_platform_info(void);
 asmlinkage void romstage_after_car(void *chipset_context);
 void romstage_common(struct romstage_params *params);
 asmlinkage void *romstage_main(struct cache_as_ram_params *car_params);
 void *setup_stack_and_mtrrs(void);
-void set_max_freq(void);
 void soc_after_ram_init(struct romstage_params *params);
 void soc_after_temp_ram_exit(void);
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index d1c846b045..a88de66441 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -29,6 +29,8 @@ void systemagent_early_init(void);
 void pch_early_init(void);
 void pch_uart_init(void);
 void intel_early_me_status(void);
+void report_platform_info(void);
+void set_max_freq(void);
 
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 0343491f3f..922062610a 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -65,6 +65,8 @@ void soc_pre_ram_init(struct romstage_params *params)
 
 void soc_romstage_init(struct romstage_params *params)
 {
+	report_platform_info();
+	set_max_freq();
 	pch_early_init();
 }