arch/riscv: Add include/arch/barrier.h

mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.

The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.

Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/include/arch/barrier.h

@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ARCH_BARRIER_H_
+#define __ARCH_BARRIER_H__
+
+static inline void mb(void)  { asm volatile("fence"); }
+static inline void rmb(void) { asm volatile("fence"); }
+static inline void wmb(void) { asm volatile("fence"); }
+
+#endif /* __ARCH_BARRIER_H__ */

src/arch/riscv/include/atomic.h

@@ -36,7 +36,6 @@
 typedef struct { int lock; } spinlock_t;
 #define SPINLOCK_INIT {0}
 
-#define mb() __sync_synchronize()
 #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
 #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
 

src/arch/riscv/virtual_memory.c

@@ -14,11 +14,12 @@
  * GNU General Public License for more details.
  */
 
-#include <vm.h>
+#include <arch/barrier.h>
 #include <arch/encoding.h>
 #include <atomic.h>
-#include <stdint.h>
 #include <console/console.h>
+#include <stdint.h>
+#include <vm.h>
 
 pte_t* root_page_table;
 

src/mainboard/emulation/qemu-riscv/qemu_util.c

@@ -25,11 +25,12 @@
  * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  */
 
-#include <spike_util.h>
+#include <arch/barrier.h>
 #include <arch/errno.h>
 #include <atomic.h>
-#include <string.h>
 #include <console/console.h>
+#include <spike_util.h>
+#include <string.h>
 
 uintptr_t translate_address(uintptr_t vAddr) {
 	// TODO: implement the page table translation algorithm

src/mainboard/emulation/spike-riscv/spike_util.c

@@ -26,6 +26,7 @@
  */
 
 #include <spike_util.h>
+#include <arch/barrier.h>
 #include <arch/errno.h>
 #include <atomic.h>
 #include <string.h>