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mb/google/dedede: Add GPE configuration 

Configure the GPIO groups to be routed to the GPE0 block.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-02-07 13:11:02 -07:00 committed by Patrick Georgi
parent 118e9755ec
commit cc633f2e3a
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
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@ -3,6 +3,22 @@ chip soc/intel/tigerlake
device lapic 0 on end device lapic 0 on end
end end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed.
# DW0 is used by:
# - GPP_B3 - TRACKPAD_INT_ODL
# - GPP_B4 - H1_AP_INT_ODL
# DW1 is used by:
# - GPP_D3 - WLAN_PCIE_WAKE_ODL
# DW2 is used by:
# - GPP_H16 - WWAN_HOST_WAKE
# EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_H"
device domain 0 on device domain 0 on
device pci 00.0 off end # Host Bridge device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device device pci 02.0 off end # Integrated Graphics Device