Add ASUS M5A88-V mainboard support
it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
2.fix some whitespace
3.fix subsystemid of devicetree.cb
Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
QingPei Wang
Stefan Reinauer
parent
914377efd6
commit
cc66d97f50
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@ -37,6 +37,8 @@ config BOARD_ASUS_M4A785M
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bool "M4A785-M"
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config BOARD_ASUS_M4A78_EM
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bool "M4A78-EM"
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config BOARD_ASUS_M5A88_V
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bool "M5A88-V"
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config BOARD_ASUS_MEW_AM
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bool "MEW-AM"
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config BOARD_ASUS_MEW_VM
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@ -64,6 +66,7 @@ source "src/mainboard/asus/m2v/Kconfig"
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source "src/mainboard/asus/m2v-mx_se/Kconfig"
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source "src/mainboard/asus/m4a785-m/Kconfig"
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source "src/mainboard/asus/m4a78-em/Kconfig"
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source "src/mainboard/asus/m5a88-v/Kconfig"
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source "src/mainboard/asus/mew-am/Kconfig"
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source "src/mainboard/asus/mew-vm/Kconfig"
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source "src/mainboard/asus/p2b/Kconfig"
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@ -0,0 +1,103 @@
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if BOARD_ASUS_M5A88_V
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_AM3
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select DIMM_DDR3
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select DIMM_REGISTERED
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select QRANK_DIMM_SUPPORT
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select NORTHBRIDGE_AMD_AMDFAM10
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select SOUTHBRIDGE_AMD_RS780
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_ITE_IT8721F
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MAINBOARD_RESOURCES
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select HAVE_HARD_RESET
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select SERIAL_CPU_INIT
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select AMDMCT
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select HAVE_MP_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_HAS_FADT
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select GENERATE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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select RAMINIT_SYSINFO
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select ENABLE_APIC_EXT_ID
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select TINY_BOOTBLOCK
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select GFXUMA
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select HAVE_DEBUG_CAR
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default asus/m5a88-v
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "M5A88PM-V"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 8
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config MEM_TRAIN_SEQ
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int
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default 2
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config AMD_UCODE_PATCH_FILE
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string
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default "mc_patch_010000bf.h"
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config RAMTOP
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hex
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default 0x2000000
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config HEAP_SIZE
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hex
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default 0xc0000
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config RAMBASE
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hex
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default 0x200000
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config VGA_BIOS_ID
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string
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default "1002,9715"
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endif #BOARD_ASUS_M5A88_V
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@ -0,0 +1,16 @@
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ramstage-y += reset.c
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#SB800 CIMx share AGESA V5 lib code
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ifneq ($(CONFIG_AMD_AGESA),y)
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AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
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romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
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ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
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AGESA_INC := -I$(AGESA_ROOT)/ \
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-I$(AGESA_ROOT)/Include \
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-I$(AGESA_ROOT)/Proc/IDS/ \
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-I$(AGESA_ROOT)/Proc/CPU/ \
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-I$(AGESA_ROOT)/Proc/CPU/Family
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CFLAGS += $(AGESA_INC)
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endif
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@ -0,0 +1,75 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This file defines the processor and performance state capability
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* for each core in the system. It is included into the DSDT for each
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* core. It assumes that each core of the system has the same performance
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* characteristics.
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*/
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/*
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DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
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{
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Scope (\_PR) {
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Processor(CPU0,0,0x808,0x06) {
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#include "cpstate.asl"
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}
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Processor(CPU1,1,0x0,0x0) {
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#include "cpstate.asl"
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}
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Processor(CPU2,2,0x0,0x0) {
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#include "cpstate.asl"
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}
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Processor(CPU3,3,0x0,0x0) {
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#include "cpstate.asl"
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}
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}
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*/
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/* P-state support: The maximum number of P-states supported by the */
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/* CPUs we'll use is 6. */
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/* Get from AMI BIOS. */
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Name(_PSS, Package(){
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Package ()
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{
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0x00000AF0,
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0x0000BF81,
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0x00000002,
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0x00000002,
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0x00000000,
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0x00000000
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},
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Package ()
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{
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0x00000578,
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0x000076F2,
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0x00000002,
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0x00000002,
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0x00000001,
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0x00000001
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}
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})
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Name(_PCT, Package(){
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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})
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Method(_PPC, 0){
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Return(0)
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}
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@ -0,0 +1,244 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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Scope (_SB) {
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Device(PCI0) {
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Device(IDEC) {
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Name(_ADR, 0x00140001)
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#include "ide.asl"
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}
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}
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}
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*/
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/* Some timing tables */
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Name(UDTT, Package(){ /* Udma timing table */
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120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
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})
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Name(MDTT, Package(){ /* MWDma timing table */
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480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
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})
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Name(POTT, Package(){ /* Pio timing table */
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600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
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})
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/* Some timing register value tables */
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Name(MDRT, Package(){ /* MWDma timing register table */
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0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
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})
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Name(PORT, Package(){
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0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
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})
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OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
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Field(ICRG, AnyAcc, NoLock, Preserve)
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{
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PPTS, 8, /* Primary PIO Slave Timing */
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PPTM, 8, /* Primary PIO Master Timing */
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OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
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PMTM, 8, /* Primary MWDMA Master Timing */
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OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
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OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
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PPSM, 4, /* Primary PIO slave Mode */
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OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
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OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
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PDSM, 4, /* Primary UltraDMA Mode */
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}
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Method(GTTM, 1) /* get total time*/
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{
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Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
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Increment(Local0)
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Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
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Increment(Local1)
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Return(Multiply(30, Add(Local0, Local1)))
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}
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Device(PRID)
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{
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Name (_ADR, Zero)
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Method(_GTM, 0)
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{
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NAME(OTBF, Buffer(20) { /* out buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
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CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
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/* Just return if the channel is disabled */
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If(And(PPCR, 0x01)) { /* primary PIO control */
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Return(OTBF)
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}
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/* Always tell them independent timing available and IOChannelReady used on both drives */
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Or(BFFG, 0x1A, BFFG)
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Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
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Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
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If(And(PDCR, 0x01)) { /* It's under UDMA mode */
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Or(BFFG, 0x01, BFFG)
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Store(DerefOf(Index(UDTT, PDMM)), DSD0)
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}
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Else {
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Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
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}
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If(And(PDCR, 0x02)) { /* It's under UDMA mode */
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Or(BFFG, 0x04, BFFG)
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Store(DerefOf(Index(UDTT, PDSM)), DSD1)
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}
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Else {
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Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
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}
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Return(OTBF) /* out buffer */
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} /* End Method(_GTM) */
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Method(_STM, 3, NotSerialized)
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{
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NAME(INBF, Buffer(20) { /* in buffer */
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
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})
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CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
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CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
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CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
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CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
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CreateDwordField(INBF, 16, BFFG) /*buffer flag */
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Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
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Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
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Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
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Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
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Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
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Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
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If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDMM,)
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Or(PDCR, 0x01, PDCR)
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}
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Else {
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If(LNotEqual(DSD0, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTM)
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}
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}
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If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
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Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Divide(Local0, 7, PDSM,)
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Or(PDCR, 0x02, PDCR)
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}
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Else {
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If(LNotEqual(DSD1, 0xFFFFFFFF)) {
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Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
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Store(DerefOf(Index(MDRT, Local0)), PMTS)
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}
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}
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/* Return(INBF) */
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} /*End Method(_STM) */
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Device(MST)
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{
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Name(_ADR, 0)
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Method(_GTF) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xA0, CMDA)
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Store(0xA0, CMDB)
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Store(0xA0, CMDC)
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Or(PPMM, 0x08, POMD)
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If(And(PDCR, 0x01)) {
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Or(PDMM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTM),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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}
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Return(CMBF)
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}
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} /* End Device(MST) */
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Device(SLAV)
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{
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Name(_ADR, 1)
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Method(_GTF) {
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Name(CMBF, Buffer(21) {
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
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})
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CreateByteField(CMBF, 1, POMD)
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CreateByteField(CMBF, 8, DMMD)
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CreateByteField(CMBF, 5, CMDA)
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CreateByteField(CMBF, 12, CMDB)
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CreateByteField(CMBF, 19, CMDC)
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Store(0xB0, CMDA)
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Store(0xB0, CMDB)
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Store(0xB0, CMDC)
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Or(PPSM, 0x08, POMD)
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If(And(PDCR, 0x02)) {
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Or(PDSM, 0x40, DMMD)
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}
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Else {
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Store(Match
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(MDTT, MLE, GTTM(PMTS),
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MTR, 0, 0), Local0)
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If(LLess(Local0, 3)) {
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Or(0x20, Local0, DMMD)
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}
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}
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Return(CMBF)
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}
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} /* End Device(SLAV) */
|
||||
}
|
||||
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "routing.asl"
|
||||
}
|
||||
*/
|
||||
|
||||
/* Routing is in System Bus scope */
|
||||
Scope(\_SB) {
|
||||
Name(PR0, Package(){
|
||||
/* NB devices */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, INTC, 0 },
|
||||
Package(){0x0002FFFF, 1, INTD, 0 },
|
||||
Package(){0x0002FFFF, 2, INTA, 0 },
|
||||
Package(){0x0002FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, INTA, 0 },
|
||||
Package(){0x0004FFFF, 1, INTB, 0 },
|
||||
Package(){0x0004FFFF, 2, INTC, 0 },
|
||||
Package(){0x0004FFFF, 3, INTD, 0 },
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
|
||||
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
|
||||
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
|
||||
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
|
||||
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
|
||||
Package(){0x0006FFFF, 0, INTC, 0 },
|
||||
Package(){0x0006FFFF, 1, INTD, 0 },
|
||||
Package(){0x0006FFFF, 2, INTA, 0 },
|
||||
Package(){0x0006FFFF, 3, INTB, 0 },
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
|
||||
Package(){0x0007FFFF, 0, INTD, 0 },
|
||||
Package(){0x0007FFFF, 1, INTA, 0 },
|
||||
Package(){0x0007FFFF, 2, INTB, 0 },
|
||||
Package(){0x0007FFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x0009FFFF, 0, INTB, 0 },
|
||||
Package(){0x0009FFFF, 1, INTC, 0 },
|
||||
Package(){0x0009FFFF, 2, INTD, 0 },
|
||||
Package(){0x0009FFFF, 3, INTA, 0 },
|
||||
|
||||
Package(){0x000AFFFF, 0, INTC, 0 },
|
||||
Package(){0x000AFFFF, 1, INTD, 0 },
|
||||
Package(){0x000AFFFF, 2, INTA, 0 },
|
||||
Package(){0x000AFFFF, 3, INTB, 0 },
|
||||
|
||||
Package(){0x000BFFFF, 0, INTD, 0 },
|
||||
Package(){0x000BFFFF, 1, INTA, 0 },
|
||||
Package(){0x000BFFFF, 2, INTB, 0 },
|
||||
Package(){0x000BFFFF, 3, INTC, 0 },
|
||||
|
||||
Package(){0x000CFFFF, 0, INTA, 0 },
|
||||
Package(){0x000CFFFF, 1, INTB, 0 },
|
||||
Package(){0x000CFFFF, 2, INTC, 0 },
|
||||
Package(){0x000CFFFF, 3, INTD, 0 },
|
||||
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, INTD, 0 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, INTC, 0 },
|
||||
Package(){0x0012FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0013FFFF, 0, INTC, 0 },
|
||||
Package(){0x0013FFFF, 1, INTB, 0 },
|
||||
|
||||
Package(){0x0016FFFF, 0, INTC, 0 },
|
||||
Package(){0x0016FFFF, 1, INTB, 0 },
|
||||
|
||||
/* Package(){0x0014FFFF, 1, INTA, 0 }, */
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
|
||||
Package(){0x0014FFFF, 0, INTA, 0 },
|
||||
Package(){0x0014FFFF, 1, INTB, 0 },
|
||||
Package(){0x0014FFFF, 2, INTC, 0 },
|
||||
Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
package(){0x0001FFFF, 1, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
/* Package(){0x0004FFFF, 1, 0, 17 }, */
|
||||
/* Package(){0x0004FFFF, 2, 0, 18 }, */
|
||||
/* Package(){0x0004FFFF, 3, 0, 19 }, */
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
/* Package(){0x0005FFFF, 0, 0, 17 }, */
|
||||
/* Package(){0x0005FFFF, 1, 0, 18 }, */
|
||||
/* Package(){0x0005FFFF, 2, 0, 19 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 16 }, */
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
/* Package(){0x0006FFFF, 0, 0, 18 }, */
|
||||
/* Package(){0x0006FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0006FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0006FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
/* Package(){0x0007FFFF, 0, 0, 19 }, */
|
||||
/* Package(){0x0007FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0007FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0007FFFF, 3, 0, 18 }, */
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
/* Package(){0x0009FFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x0009FFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x0009FFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
/* Package(){0x000AFFFF, 1, 0, 16 }, */
|
||||
/* Package(){0x000AFFFF, 2, 0, 17 }, */
|
||||
/* Package(){0x000AFFFF, 3, 0, 18 }, */
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0012FFFF, 2, 0, 18 }, */
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0013FFFF, 2, 0, 16 }, */
|
||||
|
||||
/* Package(){0x00140000, 0, 0, 16 }, */
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
|
||||
/* TODO: pcie */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0005FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0006FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0006FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0006FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0007FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0007FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0007FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* simple name description */
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
|
||||
)
|
||||
{
|
||||
#include "usb.asl"
|
||||
}
|
||||
*/
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,274 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
#include "mb_sysconf.h"
|
||||
|
||||
#define DUMP_ACPI_TABLES 0
|
||||
|
||||
#if DUMP_ACPI_TABLES == 1
|
||||
static void dump_mem(u32 start, u32 end)
|
||||
{
|
||||
|
||||
u32 i;
|
||||
print_debug("dump_mem:");
|
||||
for (i = start; i < end; i++) {
|
||||
if ((i & 0xf) == 0) {
|
||||
printk(BIOS_DEBUG, "\n%08x:", i);
|
||||
}
|
||||
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
|
||||
}
|
||||
print_debug("\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
extern const unsigned char AmlCode[];
|
||||
extern const unsigned char AmlCode_ssdt[];
|
||||
|
||||
#if CONFIG_ACPI_SSDTX_NUM >= 1
|
||||
extern const unsigned char AmlCode_ssdt2[];
|
||||
extern const unsigned char AmlCode_ssdt3[];
|
||||
extern const unsigned char AmlCode_ssdt4[];
|
||||
extern const unsigned char AmlCode_ssdt5[];
|
||||
#endif
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
/* Just a dummy */
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
|
||||
IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edige-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long write_acpi_tables(unsigned long start)
|
||||
{
|
||||
unsigned long current;
|
||||
acpi_rsdp_t *rsdp;
|
||||
acpi_rsdt_t *rsdt;
|
||||
acpi_hpet_t *hpet;
|
||||
acpi_madt_t *madt;
|
||||
acpi_srat_t *srat;
|
||||
acpi_slit_t *slit;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_facs_t *facs;
|
||||
acpi_header_t *dsdt;
|
||||
acpi_header_t *ssdt;
|
||||
#if CONFIG_ACPI_SSDTX_NUM >= 1
|
||||
acpi_header_t *ssdtx;
|
||||
void *p;
|
||||
int i;
|
||||
#endif
|
||||
|
||||
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
|
||||
|
||||
/* Align ACPI tables to 16 bytes */
|
||||
start = (start + 0x0f) & -0x10;
|
||||
current = start;
|
||||
|
||||
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt, NULL);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
|
||||
hpet = (acpi_hpet_t *) current;
|
||||
current += sizeof(acpi_hpet_t);
|
||||
acpi_create_hpet(hpet);
|
||||
acpi_add_table(rsdp, hpet);
|
||||
|
||||
/* If we want to use HPET Timers Linux wants an MADT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
|
||||
madt = (acpi_madt_t *) current;
|
||||
acpi_create_madt(madt);
|
||||
current += madt->header.length;
|
||||
acpi_add_table(rsdp, madt);
|
||||
|
||||
/* SRAT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
|
||||
srat = (acpi_srat_t *) current;
|
||||
acpi_create_srat(srat);
|
||||
current += srat->header.length;
|
||||
acpi_add_table(rsdp, srat);
|
||||
|
||||
/* SLIT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
|
||||
slit = (acpi_slit_t *) current;
|
||||
acpi_create_slit(slit);
|
||||
current += slit->header.length;
|
||||
acpi_add_table(rsdp, slit);
|
||||
|
||||
/* SSDT */
|
||||
current = ( current + 0x0f) & -0x10;
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
|
||||
ssdt = (acpi_header_t *)current;
|
||||
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
|
||||
current += ssdt->length;
|
||||
memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
|
||||
//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
|
||||
update_ssdt((void*)ssdt);
|
||||
/* recalculate checksum */
|
||||
ssdt->checksum = 0;
|
||||
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
|
||||
acpi_add_table(rsdp,ssdt);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
|
||||
current = acpi_add_ssdt_pstates(rsdp, current);
|
||||
|
||||
#if CONFIG_ACPI_SSDTX_NUM >= 1
|
||||
|
||||
/* same htio, but different position? We may have to copy,
|
||||
change HCIN, and recalculate the checknum and add_table */
|
||||
|
||||
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
|
||||
if((sysconf.pci1234[i] & 1) != 1 ) continue;
|
||||
u8 c;
|
||||
if (i < 7) {
|
||||
c = (u8) ('4' + i - 1);
|
||||
} else {
|
||||
c = (u8) ('A' + i - 1 - 6);
|
||||
}
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
|
||||
ssdtx = (acpi_header_t *)current;
|
||||
switch (sysconf.hcid[i]) {
|
||||
case 1:
|
||||
p = &AmlCode_ssdt2;
|
||||
break;
|
||||
case 2:
|
||||
p = &AmlCode_ssdt3;
|
||||
break;
|
||||
case 3: /* 8131 */
|
||||
p = &AmlCode_ssdt4;
|
||||
break;
|
||||
default:
|
||||
/* HTX no io apic */
|
||||
p = &AmlCode_ssdt5;
|
||||
break;
|
||||
}
|
||||
memcpy(ssdtx, p, sizeof(acpi_header_t));
|
||||
current += ssdtx->length;
|
||||
memcpy(ssdtx, p, ssdtx->length);
|
||||
update_ssdtx((void *)ssdtx, i);
|
||||
ssdtx->checksum = 0;
|
||||
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
|
||||
acpi_add_table(rsdp, ssdtx);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* DSDT */
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
|
||||
dsdt = (acpi_header_t *)current; // it will used by fadt
|
||||
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
|
||||
current += dsdt->length;
|
||||
memcpy(dsdt, &AmlCode, dsdt->length);
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
|
||||
|
||||
/* FACS */ // it needs 64 bit alignment
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
|
||||
facs = (acpi_facs_t *) current; // it will be used by fadt
|
||||
current += sizeof(acpi_facs_t);
|
||||
acpi_create_facs(facs);
|
||||
|
||||
/* FDAT */
|
||||
#if CONFIG_BOARD_HAS_FADT == 1
|
||||
current = ( current + 0x07) & -0x08;
|
||||
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
|
||||
acpi_create_fadt(fadt, facs, dsdt);
|
||||
acpi_add_table(rsdp, fadt);
|
||||
#endif
|
||||
|
||||
#if DUMP_ACPI_TABLES == 1
|
||||
printk(BIOS_DEBUG, "rsdp\n");
|
||||
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
|
||||
|
||||
printk(BIOS_DEBUG, "rsdt\n");
|
||||
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
|
||||
|
||||
printk(BIOS_DEBUG, "madt\n");
|
||||
dump_mem(madt, ((void *)madt) + madt->header.length);
|
||||
|
||||
printk(BIOS_DEBUG, "srat\n");
|
||||
dump_mem(srat, ((void *)srat) + srat->header.length);
|
||||
|
||||
printk(BIOS_DEBUG, "slit\n");
|
||||
dump_mem(slit, ((void *)slit) + slit->header.length);
|
||||
|
||||
printk(BIOS_DEBUG, "ssdt\n");
|
||||
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
|
||||
|
||||
printk(BIOS_DEBUG, "fadt\n");
|
||||
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
|
||||
#endif
|
||||
|
||||
printk(BIOS_INFO, "ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_ops;
|
||||
|
||||
struct mainboard_config {};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
# sample config for advansus/A785E-I
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/amd/socket_AM3 #L1 and DDR3
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id.
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
chip southbridge/amd/rs780
|
||||
device pci 0.0 on end # HT 0x9600
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x960b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
|
||||
device pci 5.0 off end # PCIE P2P bridge 0x9605
|
||||
device pci 6.0 off end # PCIE P2P bridge 0x9606
|
||||
device pci 7.0 off end # PCIE P2P bridge 0x9607
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
device pci 9.0 on end # Ethernet
|
||||
device pci a.0 on end # Ethernet
|
||||
register "gppsb_configuration" = "4" # Configuration E
|
||||
register "gpp_configuration" = "3" # Configuration D
|
||||
register "port_enable" = "0x6f6"
|
||||
register "gfx_dev2_dev3" = "0"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
register "gfx_tmds" = "1"
|
||||
register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
|
||||
register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
|
||||
end
|
||||
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on
|
||||
chip superio/ite/it8721f
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # SFI
|
||||
io 0x62 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GPIO_GAME_MIDI
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # WDTO_PLED
|
||||
device pnp 2e.9 off end # GPIO_SUSLED
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end #superio/winbond/w83627hf
|
||||
end # LPC 0x439d
|
||||
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.6 off end # Gec
|
||||
device pci 15.0 on end # PCIe 0
|
||||
device pci 15.1 on end # PCIe 1
|
||||
device pci 15.2 on end # PCIe 2
|
||||
device pci 15.3 on end # PCIe 3
|
||||
device pci 16.0 on end # USB
|
||||
device pci 16.2 on end # USB
|
||||
#register "gpp_configuration" = "0" #4:0:0:0
|
||||
#register "gpp_configuration" = "2" #2:2:0:0
|
||||
#register "gpp_configuration" = "3" #2:1:1:0
|
||||
register "gpp_configuration" = "4" #1:1:1:1
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
end #southbridge/amd/cimx/sb800
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
end
|
||||
end #pci_domain
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* ACPI - create the Fixed ACPI Description Tables (FADT)
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include "SBPLATFORM.h"
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
u16 val;
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
|
||||
|
||||
/* Prepare the header */
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = 244;
|
||||
header->revision = 3;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, "COREBOOT", 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
header->asl_compiler_revision = 0;
|
||||
|
||||
fadt->firmware_ctrl = (u32) facs;
|
||||
fadt->dsdt = (u32) dsdt;
|
||||
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
|
||||
fadt->preferred_pm_profile = 0x03;
|
||||
fadt->sci_int = 9;
|
||||
/* disable system management mode by setting to 0: */
|
||||
fadt->smi_cmd = 0;
|
||||
fadt->acpi_enable = 0xf0;
|
||||
fadt->acpi_disable = 0xf1;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0xe2;
|
||||
|
||||
val = PM1_EVT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
|
||||
val = PM1_CNT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
|
||||
val = PM1_TMR_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
|
||||
val = GPE0_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
|
||||
|
||||
/* CpuControl is in \_PR.CPU0, 6 bytes */
|
||||
val = CPU_CNT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
|
||||
val = 0;
|
||||
WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
|
||||
val = ACPI_PMA_CNT_BLK_ADDRESS;
|
||||
WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
|
||||
|
||||
/* AcpiDecodeEnable, When set, SB uses the contents of the
|
||||
* PM registers at index 60-6B to decode ACPI I/O address.
|
||||
* AcpiSmiEn & SmiCmdEn
|
||||
*/
|
||||
val = BIT0 | BIT1 | BIT2 | BIT4;
|
||||
WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
|
||||
|
||||
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
|
||||
outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */
|
||||
|
||||
fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
|
||||
fadt->pm1b_evt_blk = 0x0000;
|
||||
fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
|
||||
fadt->pm1b_cnt_blk = 0x0000;
|
||||
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
|
||||
fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
|
||||
fadt->gpe0_blk = GPE0_BLK_ADDRESS;
|
||||
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 8;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
|
||||
fadt->cst_cnt = 0xe3;
|
||||
fadt->p_lvl2_lat = 101;
|
||||
fadt->p_lvl3_lat = 1001;
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 3;
|
||||
fadt->day_alrm = 0; /* 0x7d these have to be */
|
||||
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
|
||||
fadt->century = 0; /* 0x7f to make rtc alrm work */
|
||||
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
|
||||
fadt->flags = 0x0001c1a5;/* 0x25; */
|
||||
|
||||
fadt->res2 = 0;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0x0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (u32) facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (u32) dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 4;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 32;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
|
||||
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
|
||||
}
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include <cpu/amd/multicore.h>
|
||||
#endif
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#if CONFIG_AMD_SB_CIMX
|
||||
#include <sb_cimx.h>
|
||||
#endif
|
||||
|
||||
/* Global variables for MB layouts and these will be shared by irqtable mptable
|
||||
* and acpi_tables busnum is default.
|
||||
*/
|
||||
int bus_isa;
|
||||
u8 bus_rs780[11];
|
||||
u8 bus_sb800[3];
|
||||
u32 apicid_sb800;
|
||||
|
||||
/*
|
||||
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
* You may need to preset pci1234 for HTIO board,
|
||||
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
*/
|
||||
u32 pci1234x[] = {
|
||||
0x0000ff0,
|
||||
};
|
||||
|
||||
/*
|
||||
* HT Chain device num, actually it is unit id base of every ht device in chain,
|
||||
* assume every chain only have 4 ht device at most
|
||||
*/
|
||||
u32 hcdnx[] = {
|
||||
0x20202020,
|
||||
};
|
||||
|
||||
u32 bus_type[256];
|
||||
|
||||
u32 sbdn_rs780;
|
||||
u32 sbdn_sb800;
|
||||
|
||||
extern void get_pci1234(void);
|
||||
|
||||
static u32 get_bus_conf_done = 0;
|
||||
|
||||
void get_bus_conf(void)
|
||||
{
|
||||
u32 apicid_base;
|
||||
device_t dev;
|
||||
int i, j;
|
||||
|
||||
if (get_bus_conf_done == 1)
|
||||
return; /* do it only once */
|
||||
get_bus_conf_done = 1;
|
||||
|
||||
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
|
||||
for (i = 0; i < sysconf.hc_possible_num; i++) {
|
||||
sysconf.pci1234[i] = pci1234x[i];
|
||||
sysconf.hcdn[i] = hcdnx[i];
|
||||
}
|
||||
|
||||
get_pci1234();
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
|
||||
sbdn_rs780 = sysconf.sbdn;
|
||||
sbdn_sb800 = 0;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
bus_sb800[i] = 0;
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
bus_rs780[i] = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
bus_type[i] = 0; /* default ISA bus. */
|
||||
}
|
||||
|
||||
bus_type[0] = 1; /* pci */
|
||||
|
||||
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
|
||||
bus_sb800[0] = bus_rs780[0];
|
||||
|
||||
bus_type[bus_rs780[0]] = 1;
|
||||
|
||||
/* sb800 */
|
||||
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
|
||||
if (dev) {
|
||||
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
for (j = bus_sb800[1]; j < bus_isa; j++)
|
||||
bus_type[j] = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x15, i));
|
||||
if (dev) {
|
||||
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
}
|
||||
for (j = bus_sb800[2]; j < bus_isa; j++)
|
||||
bus_type[j] = 1;
|
||||
|
||||
/* rs780 */
|
||||
for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
|
||||
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
|
||||
if (dev) {
|
||||
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
if(255 != bus_rs780[i]) {
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
bus_type[bus_rs780[i]] = 1; /* PCI bus. */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
bus_isa = 10;
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(1);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_sb800 = apicid_base + 0;
|
||||
|
||||
#if CONFIG_AMD_SB_CIMX
|
||||
sb_Late_Post();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern u8 bus_isa;
|
||||
extern u8 bus_rs780[8];
|
||||
extern u8 bus_sb800[2];
|
||||
extern unsigned long sbdn_sb800;
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = bus_sb800[0];
|
||||
pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <boot/tables.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/pci_def.h>
|
||||
#include "SBPLATFORM.h"
|
||||
#include "chip.h"
|
||||
|
||||
uint64_t uma_memory_base, uma_memory_size;
|
||||
|
||||
u8 is_dev3_present(void);
|
||||
void set_pcie_dereset(void);
|
||||
void set_pcie_reset(void);
|
||||
void enable_int_gfx(void);
|
||||
|
||||
/* GPIO6. */
|
||||
void enable_int_gfx(void)
|
||||
{
|
||||
volatile u8 *gpio_reg;
|
||||
|
||||
#ifdef UNUSED_CODE
|
||||
RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
|
||||
RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
|
||||
#endif
|
||||
/* make sure the MMIO(fed80000) is accessible */
|
||||
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
|
||||
|
||||
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
|
||||
*(gpio_reg + 170) = 0x1; /* gpio_gate */
|
||||
|
||||
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
|
||||
|
||||
*(gpio_reg + 0x6) = 0x8;
|
||||
*(gpio_reg + 170) = 0x0;
|
||||
}
|
||||
|
||||
void set_pcie_dereset()
|
||||
{
|
||||
}
|
||||
|
||||
void set_pcie_reset(void)
|
||||
{
|
||||
}
|
||||
|
||||
u8 is_dev3_present(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*************************************************
|
||||
* enable the dedicated function in M5A88-V board.
|
||||
* This function called early than rs780_enable.
|
||||
*************************************************/
|
||||
static void m5a88pm_v_enable(device_t dev)
|
||||
{
|
||||
|
||||
printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
|
||||
|
||||
#if (CONFIG_GFXUMA == 1)
|
||||
msr_t msr, msr2;
|
||||
|
||||
/* TOP_MEM: the top of DRAM below 4G */
|
||||
msr = rdmsr(TOP_MEM);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
|
||||
__func__, msr.lo, msr.hi);
|
||||
|
||||
/* TOP_MEM2: the top of DRAM above 4G */
|
||||
msr2 = rdmsr(TOP_MEM2);
|
||||
printk
|
||||
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
|
||||
__func__, msr2.lo, msr2.hi);
|
||||
|
||||
/* refer to UMA Size Consideration in 780 BDG. */
|
||||
switch (msr.lo) {
|
||||
case 0x10000000: /* 256M system memory */
|
||||
uma_memory_size = 0x4000000; /* 64M recommended UMA */
|
||||
break;
|
||||
|
||||
case 0x20000000: /* 512M system memory */
|
||||
uma_memory_size = 0x8000000; /* 128M recommended UMA */
|
||||
break;
|
||||
|
||||
default: /* 1GB and above system memory */
|
||||
uma_memory_size = 0x10000000; /* 256M recommended UMA */
|
||||
break;
|
||||
}
|
||||
|
||||
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
|
||||
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
|
||||
__func__, uma_memory_size, uma_memory_base);
|
||||
|
||||
/* TODO: TOP_MEM2 */
|
||||
#else
|
||||
uma_memory_size = 0x8000000; /* 128M recommended UMA */
|
||||
uma_memory_base = 0x38000000; /* 1GB system memory supposed */
|
||||
#endif
|
||||
|
||||
set_pcie_dereset();
|
||||
enable_int_gfx();
|
||||
}
|
||||
|
||||
int add_mainboard_resources(struct lb_memory *mem)
|
||||
{
|
||||
/* UMA is removed from system memory in the northbridge code, but
|
||||
* in some circumstances we want the memory mentioned as reserved.
|
||||
*/
|
||||
#if (CONFIG_GFXUMA == 1)
|
||||
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
|
||||
uma_memory_base, uma_memory_size);
|
||||
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
|
||||
uma_memory_size);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("ASUS M5A88-V Mainboard")
|
||||
.enable_dev = m5a88pm_v_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef MB_SYSCONF_H
|
||||
#define MB_SYSCONF_H
|
||||
|
||||
struct mb_sysconf_t {
|
||||
u8 bus_isa;
|
||||
u8 bus_8132_0;
|
||||
u8 bus_8132_1;
|
||||
u8 bus_8132_2;
|
||||
u8 bus_8111_0;
|
||||
u8 bus_8111_1;
|
||||
u8 bus_8132a[31][3];
|
||||
u8 bus_8151[31][2];
|
||||
|
||||
u32 apicid_8111;
|
||||
u32 apicid_8132_1;
|
||||
u32 apicid_8132_2;
|
||||
u32 apicid_8132a[31][2];
|
||||
u32 sbdn3;
|
||||
u32 sbdn3a[31];
|
||||
u32 sbdn5[31];
|
||||
u32 bus_type[256];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <cpu/amd/amdfam10_sysconf.h>
|
||||
#include <SBPLATFORM.h>
|
||||
|
||||
extern int bus_isa;
|
||||
extern u8 bus_rs780[11];
|
||||
extern u8 bus_sb800[2];
|
||||
extern u32 apicid_sb800;
|
||||
extern u32 bus_type[256];
|
||||
extern u32 sbdn_rs780;
|
||||
extern u32 sbdn_sb800;
|
||||
|
||||
u8 intr_data[] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
u32 dword;
|
||||
u8 byte;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LAPIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
|
||||
dword &= 0xFFFFFFF0;
|
||||
smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#if CONFIG_GENERATE_ACPI_TABLES == 0
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
|
||||
#else
|
||||
#define PCI_INT(bus, dev, fn, pin)
|
||||
#endif
|
||||
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
|
||||
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
|
||||
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
|
||||
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
|
||||
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
|
||||
/* configuration B doesnt need dev 5,6,7 */
|
||||
/*
|
||||
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
|
||||
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
|
||||
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
|
||||
*/
|
||||
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
|
||||
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
|
||||
|
||||
/* PCI slots */
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum =
|
||||
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _M5A88_V_CFG_H_
|
||||
#define _M5A88_V_CFG_H_
|
||||
|
||||
/**
|
||||
* @def BIOS_SIZE_1M
|
||||
* @def BIOS_SIZE_2M
|
||||
* @def BIOS_SIZE_4M
|
||||
* @def BIOS_SIZE_8M
|
||||
*/
|
||||
#define BIOS_SIZE_1M 0
|
||||
#define BIOS_SIZE_2M 1
|
||||
#define BIOS_SIZE_4M 3
|
||||
#define BIOS_SIZE_8M 7
|
||||
|
||||
/* In SB800, default ROM size is 1M Bytes, if your platform ROM
|
||||
* bigger than 1M you have to set the ROM size outside CIMx module and
|
||||
* before AGESA module get call.
|
||||
*/
|
||||
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
|
||||
#define BIOS_SIZE BIOS_SIZE_1M
|
||||
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
|
||||
#define BIOS_SIZE BIOS_SIZE_2M
|
||||
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
|
||||
#define BIOS_SIZE BIOS_SIZE_4M
|
||||
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
|
||||
#define BIOS_SIZE BIOS_SIZE_8M
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @def SPREAD_SPECTRUM
|
||||
* @brief
|
||||
* 0 - Disable Spread Spectrum function
|
||||
* 1 - Enable Spread Spectrum function
|
||||
*/
|
||||
#define SPREAD_SPECTRUM 0
|
||||
|
||||
/**
|
||||
* @def SB_HPET_TIMER
|
||||
* @breif
|
||||
* 0 - Disable hpet
|
||||
* 1 - Enable hpet
|
||||
*/
|
||||
#define HPET_TIMER 1
|
||||
|
||||
/**
|
||||
* @def USB_CONFIG
|
||||
* @brief bit[0-6] used to control USB
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
* Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
|
||||
* Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
|
||||
* Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
|
||||
* Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
|
||||
* Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
|
||||
* Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
|
||||
* Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
|
||||
*/
|
||||
#define USB_CONFIG 0x7F
|
||||
|
||||
/**
|
||||
* @def PCI_CLOCK_CTRL
|
||||
* @breif bit[0-4] used for PCI Slots Clock Control,
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
* PCI SLOT 0 define at BIT0
|
||||
* PCI SLOT 1 define at BIT1
|
||||
* PCI SLOT 2 define at BIT2
|
||||
* PCI SLOT 3 define at BIT3
|
||||
* PCI SLOT 4 define at BIT4
|
||||
*/
|
||||
#define PCI_CLOCK_CTRL 0x1F
|
||||
|
||||
/**
|
||||
* @def SATA_CONTROLLER
|
||||
* @breif INCHIP Sata Controller
|
||||
*/
|
||||
#define SATA_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def SATA_MODE
|
||||
* @breif INCHIP Sata Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_MODE NATIVE_IDE_MODE
|
||||
|
||||
/**
|
||||
* @breif INCHIP Sata IDE Controller Mode
|
||||
*/
|
||||
#define IDE_LEGACY_MODE 0
|
||||
#define IDE_NATIVE_MODE 1
|
||||
|
||||
/**
|
||||
* @def SATA_IDE_MODE
|
||||
* @breif INCHIP Sata IDE Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_IDE_MODE IDE_LEGACY_MODE
|
||||
|
||||
/**
|
||||
* @def EXTERNAL_CLOCK
|
||||
* @brief 00/10: Reference clock from crystal oscillator via
|
||||
* PAD_XTALI and PAD_XTALO
|
||||
*
|
||||
* @def INTERNAL_CLOCK
|
||||
* @brief 01/11: Reference clock from internal clock through
|
||||
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
|
||||
*/
|
||||
#define EXTERNAL_CLOCK 0x00
|
||||
#define INTERNAL_CLOCK 0x01
|
||||
|
||||
/* NOTE: inagua have to using internal clock,
|
||||
* otherwise can not detect sata drive
|
||||
*/
|
||||
#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
|
||||
|
||||
/**
|
||||
* @def SATA_PORT_MULT_CAP_RESERVED
|
||||
* @brief 1 ON, 0 0FF
|
||||
*/
|
||||
#define SATA_PORT_MULT_CAP_RESERVED 1
|
||||
|
||||
|
||||
/**
|
||||
* @def AZALIA_AUTO
|
||||
* @brief Detect Azalia controller automatically.
|
||||
*
|
||||
* @def AZALIA_DISABLE
|
||||
* @brief Disable Azalia controller.
|
||||
|
||||
* @def AZALIA_ENABLE
|
||||
* @brief Enable Azalia controller.
|
||||
*/
|
||||
#define AZALIA_AUTO 0
|
||||
#define AZALIA_DISABLE 1
|
||||
#define AZALIA_ENABLE 2
|
||||
|
||||
/**
|
||||
* @breif INCHIP HDA controller
|
||||
*/
|
||||
#define AZALIA_CONTROLLER AZALIA_AUTO
|
||||
|
||||
/**
|
||||
* @def AZALIA_PIN_CONFIG
|
||||
* @brief
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
*/
|
||||
#define AZALIA_PIN_CONFIG 1
|
||||
|
||||
/**
|
||||
* @def AZALIA_SDIN_PIN
|
||||
* @brief
|
||||
* SDIN0 is define at BIT0 & BIT1
|
||||
* 00 - GPIO PIN
|
||||
* 01 - Reserved
|
||||
* 10 - As a Azalia SDIN pin
|
||||
* SDIN1 is define at BIT2 & BIT3
|
||||
* SDIN2 is define at BIT4 & BIT5
|
||||
* SDIN3 is define at BIT6 & BIT7
|
||||
*/
|
||||
//#define AZALIA_SDIN_PIN 0xAA
|
||||
#define AZALIA_SDIN_PIN 0x2A
|
||||
|
||||
/**
|
||||
* @def GPP_CONTROLLER
|
||||
*/
|
||||
#define GPP_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def GPP_CFGMODE
|
||||
* @brief GPP Link Configuration
|
||||
* four possible configuration:
|
||||
* GPP_CFGMODE_X4000
|
||||
* GPP_CFGMODE_X2200
|
||||
* GPP_CFGMODE_X2110
|
||||
* GPP_CFGMODE_X1111
|
||||
*/
|
||||
#define GPP_CFGMODE GPP_CFGMODE_X1111
|
||||
|
||||
/**
|
||||
* @def NB_SB_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define NB_SB_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define SB_GPP_GEN2 TRUE
|
||||
|
||||
|
||||
/**
|
||||
* @def GEC_CONFIG
|
||||
* 0 - Enable
|
||||
* 1 - Disable
|
||||
*/
|
||||
#define GEC_CONFIG 0
|
||||
|
||||
/**
|
||||
* @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
|
||||
*/
|
||||
#define SIO_HWM_BASE_ADDRESS 0x290
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <reset.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
|
||||
#define HT_INIT_CONTROL 0x6C
|
||||
#define HTIC_BIOSR_Detect (1<<5)
|
||||
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 32
|
||||
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
|
||||
#else
|
||||
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
|
||||
#endif
|
||||
|
||||
static inline void set_bios_reset(void)
|
||||
{
|
||||
u32 nodes, htic;
|
||||
device_t dev;
|
||||
int i;
|
||||
|
||||
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
|
||||
for (i = 0; i < nodes; i++) {
|
||||
dev = NODE_PCI(i, 0);
|
||||
htic = pci_read_config32(dev, HT_INIT_CONTROL);
|
||||
htic &= ~HTIC_BIOSR_Detect;
|
||||
pci_write_config32(dev, HT_INIT_CONTROL, htic);
|
||||
}
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
/* Try rebooting through port 0xcf9 */
|
||||
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
|
||||
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
|
||||
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
|
||||
}
|
||||
|
||||
//SbReset();
|
||||
void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
/* link reset */
|
||||
outb(0x06, 0x0cf9);
|
||||
}
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
static void setup_mb_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
* F1:0x4C i = 1
|
||||
* F1:0x54 i = 2
|
||||
* F1:0x5C i = 3
|
||||
* F1:0x64 i = 4
|
||||
* F1:0x6C i = 5
|
||||
* F1:0x74 i = 6
|
||||
* F1:0x7C i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 3] Reserved
|
||||
* [10: 8] Interleave select
|
||||
* specifies the values of A[14:12] to use with interleave enable.
|
||||
* [15:11] Reserved
|
||||
* [31:16] DRAM Limit Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
|
||||
int max;
|
||||
max = ARRAY_SIZE(register_values);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
//#define SYSTEM_TYPE 0 /* SERVER */
|
||||
#define SYSTEM_TYPE 1 /* DESKTOP */
|
||||
//#define SYSTEM_TYPE 2 /* MOBILE */
|
||||
|
||||
//used by incoherent_ht
|
||||
#define FAM10_SCAN_PCI_BUS 0
|
||||
#define FAM10_ALLOCATE_IO_RANGE 0
|
||||
|
||||
#include <lib.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/model_10xxx_rev.h>
|
||||
#include "northbridge/amd/amdfam10/raminit.h"
|
||||
#include "northbridge/amd/amdfam10/amdfam10.h"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdfam10/reset_test.c"
|
||||
#include <console/loglevel.h>
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "superio/ite/it8721f/early_serial.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
||||
#include "southbridge/amd/rs780/early_setup.c"
|
||||
#include <sb_cimx.h>
|
||||
#include <SBPLATFORM.h> /* SB OEM constants */
|
||||
#include <southbridge/amd/cimx/sb800/smbus.h>
|
||||
#include "northbridge/amd/amdfam10/debug.c"
|
||||
|
||||
static void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
static int spd_read_byte(u32 device, u32 address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
|
||||
#include "northbridge/amd/amdfam10/pci.c"
|
||||
#include "resourcemap.c"
|
||||
#include "cpu/amd/quadcore/quadcore.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
#include "cpu/amd/microcode/microcode.c"
|
||||
#if CONFIG_UPDATE_CPU_MICROCODE
|
||||
#include "cpu/amd/model_10xxx/update_microcode.c"
|
||||
#endif
|
||||
#include "cpu/amd/model_10xxx/init_cpus.c"
|
||||
#include "northbridge/amd/amdfam10/early_ht.c"
|
||||
#include "spd.h"
|
||||
|
||||
#include <reset.h>
|
||||
void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
/* link reset */
|
||||
outb(0x06, 0x0cf9);
|
||||
}
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
|
||||
u32 bsp_apicid = 0, val;
|
||||
msr_t msr;
|
||||
|
||||
if (!cpu_init_detectedx && boot_cpu()) {
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* mov bsp to bus 0xff when > 8 nodes */
|
||||
set_bsp_node_CHtExtNodeCfgEn();
|
||||
enumerate_ht_chain();
|
||||
|
||||
//enable port80 decoding and southbridge poweron init
|
||||
sb_Poweron_Init();
|
||||
}
|
||||
|
||||
post_code(0x30);
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
|
||||
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
|
||||
enable_rs780_dev8();
|
||||
sb800_clk_output_48Mhz();
|
||||
|
||||
it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
// Load MPB
|
||||
val = cpuid_eax(1);
|
||||
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
|
||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
||||
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
|
||||
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
|
||||
|
||||
/* Setup sysinfo defaults */
|
||||
set_sysinfo_in_ram(0);
|
||||
|
||||
#if CONFIG_UPDATE_CPU_MICROCODE
|
||||
update_microcode(val);
|
||||
#endif
|
||||
post_code(0x33);
|
||||
|
||||
cpuSetAMDMSR();
|
||||
post_code(0x34);
|
||||
|
||||
amd_ht_init(sysinfo);
|
||||
post_code(0x35);
|
||||
|
||||
/* Setup nodes PCI space and start core 0 AP init. */
|
||||
finalize_node_setup(sysinfo);
|
||||
|
||||
/* Setup any mainboard PCI settings etc. */
|
||||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
It would be nice to fixup prink spinlocks for ROM XIP mode.
|
||||
I think it could be done by putting the spinlock flag in the cache
|
||||
of the BSP located right after sysinfo.
|
||||
*/
|
||||
wait_all_core0_started();
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores();
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
/* run _early_setup before soft-reset. */
|
||||
rs780_early_setup();
|
||||
|
||||
#if CONFIG_SET_FIDVID == 1
|
||||
msr = rdmsr(0xc0010071);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
post_code(0x39);
|
||||
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
/* show final fid and vid */
|
||||
msr=rdmsr(0xc0010071);
|
||||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
|
||||
#endif
|
||||
|
||||
rs780_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
print_info("...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset_x - shouldn't see this message!!!\n");
|
||||
}
|
||||
|
||||
post_code(0x3B);
|
||||
|
||||
/* It's the time to set ctrl in sysinfo now; */
|
||||
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
post_code(0x40);
|
||||
|
||||
// die("Die Before MCT init.");
|
||||
|
||||
printk(BIOS_DEBUG, "raminit_amdmct()\n");
|
||||
raminit_amdmct(sysinfo);
|
||||
post_code(0x41);
|
||||
|
||||
/*
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
|
||||
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
|
||||
*/
|
||||
|
||||
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
|
||||
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
|
||||
|
||||
// die("After MCT init before CAR disabled.");
|
||||
|
||||
rs780_before_pci_init();
|
||||
|
||||
post_code(0x42);
|
||||
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
|
||||
post_code(0x43); // Should never see this post code.
|
||||
}
|
||||
|
||||
/**
|
||||
* BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
|
||||
* Description:
|
||||
* This routine is called every time a non-coherent chain is processed.
|
||||
* BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
|
||||
* swap list. The first part of the list controls the BUID assignment and the
|
||||
* second part of the list provides the device to device linking. Device orientation
|
||||
* can be detected automatically, or explicitly. See documentation for more details.
|
||||
*
|
||||
* Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
|
||||
* based on each device's unit count.
|
||||
*
|
||||
* Parameters:
|
||||
* @param[in] u8 node = The node on which this chain is located
|
||||
* @param[in] u8 link = The link on the host for this chain
|
||||
* @param[out] u8** list = supply a pointer to a list
|
||||
* @param[out] BOOL result = true to use a manual list
|
||||
* false to initialize the link automatically
|
||||
*/
|
||||
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
|
||||
{
|
||||
static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
|
||||
/* If the BUID was adjusted in early_ht we need to do the manual override */
|
||||
if ((node == 0) && (link == 0)) { /* BSP SB link */
|
||||
*List = swaplist;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue