GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/stoneyridge: Add PMxC0 reset status to boot log 

Print the PMxC0 S5/Reset status bits to the console.

TEST=Inspect console for Grunt
BUG=b:110788201

Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Edward Hill 2018-08-10 16:20:02 -06:00 committed by Patrick Georgi
parent f716f2ac1a
commit cc68034ee9
2 changed files with 58 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -91,6 +91,7 @@
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe #define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5) #define SLPTYPE_CONTROL_EN BIT(5)
#define PM_RST_STATUS 0xc0
#define PM_PMIO_DEBUG 0xd2 #define PM_PMIO_DEBUG 0xd2
#define PM_MANUAL_RESET 0xd3 #define PM_MANUAL_RESET 0xd3
#define PM_HUD_SD_FLASH_CTRL 0xe7 #define PM_HUD_SD_FLASH_CTRL 0xe7

76
src/soc/amd/stoneyridge/southbridge.c
View File

@ -644,8 +644,64 @@ void bootblock_fch_early_init(void)
enable_aoac_devices(); enable_aoac_devices();
} }
static void print_num_status_bits(int num_bits, uint32_t status,
const char *const bit_names[])
{
int i;
if (!status)
return;
for (i = num_bits - 1; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
else
printk(BIOS_DEBUG, "BIT%d ", i);
}
}
}
static void sb_print_pmxc0_status(void)
{
/* PMxC0 S5/Reset Status shows the source of previous reset. */
uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
static const char *const pmxc0_status_bits[] = {
[0] = "ThermalTrip",
[1] = "FourSecondPwrBtn",
[2] = "Shutdown",
[3] = "ThermalTripFromTemp",
[4] = "RemotePowerDownFromASF",
[5] = "ShutDownFan0",
[16] = "UserRst",
[17] = "SoftPciRst",
[18] = "DoInit",
[19] = "DoReset",
[20] = "DoFullReset",
[21] = "SleepReset",
[22] = "KbReset",
[23] = "LtReset",
[24] = "FailBootRst",
[25] = "WatchdogIssueReset",
[26] = "RemoteResetFromASF",
[27] = "SyncFlood",
[28] = "HangReset",
[29] = "EcWatchdogRst",
[31] = "BIT31",
};
printk(BIOS_SPEW, "PMxC0 STATUS: 0x%x ", pmxc0_status);
print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
pmxc0_status_bits);
printk(BIOS_SPEW, "\n");
}
/* After console init */ /* After console init */
void bootblock_fch_init(void) {} void bootblock_fch_init(void)
{
sb_print_pmxc0_status();
}
void sb_enable(device_t dev) void sb_enable(device_t dev)
{ {
@ -698,24 +754,6 @@ static void sb_init_acpi_ports(void)
PM_ACPI_TIMER_EN_EN); PM_ACPI_TIMER_EN_EN);
} }
static void print_num_status_bits(int num_bits, uint32_t status,
const char *const bit_names[])
{
int i;
if (!status)
return;
for (i = num_bits - 1; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
else
printk(BIOS_DEBUG, "BIT%d ", i);
}
}
}
static uint16_t reset_pm1_status(void) static uint16_t reset_pm1_status(void)
{ {
uint16_t pm1_sts = inw(ACPI_PM1_STS); uint16_t pm1_sts = inw(ACPI_PM1_STS);