mb/google/octopus: Configure PCH_WP_OD early.
The GPIO for EEPROM write-protect should be configured early, before romstage. This change configures that pad earlier. This pad is the same on the existing Octopus schematics. BUG=None TEST=None Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -236,7 +236,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_DATA */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_190, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_1 */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */
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@ -264,6 +263,7 @@ const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
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/* GPIOs needed prior to ramstage. */
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
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};
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const struct pad_config *__attribute__((weak))
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