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mb/google/octopus: Configure PCH_WP_OD early. 

The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.

BUG=None
TEST=None

Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Justin TerAvest 2018-03-16 13:29:42 -06:00 committed by Martin Roth
parent f12bb7bcf2
commit cc6953bb34
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/octopus/variants/baseboard/gpio.c
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@ -236,7 +236,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_DATA */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_DATA */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_190, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_1 */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */
@ -264,6 +263,7 @@ const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
/* GPIOs needed prior to ramstage. */ /* GPIOs needed prior to ramstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
}; };
const struct pad_config *__attribute__((weak)) const struct pad_config *__attribute__((weak))