mb/google/zork: Switch USI_RESET to active low polarity for v3.6+

v3.6 of reference schematics have switched the polarity of reset
signal to touchscreen controller from active high to active low. This
change updates the default configuration in baseboard gpio tables to
set the reset GPIO to output low and override tables in variants to set the
reset GPIO to output high. Additionally, devicetree by default exposes
ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6
boards, reset GPIO is updated to ACTIVE_HIGH based on board version.

BUG=b:161937506

Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/zork/mainboard.c

@@ -136,6 +136,7 @@ static void mainboard_devtree_update(void)
 {
 	variant_audio_update();
 	variant_bluetooth_update();
+	variant_touchscreen_update();
 	variant_devtree_update();
 }
 

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

@@ -150,8 +150,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 	/* DEV_BEEP_BCLK */
 	PAD_GPI(GPIO_139, PULL_NONE),
-	/* USI_RESET */
-	PAD_GPO(GPIO_140, HIGH),
+	/* USI_RESET_L */
+	PAD_GPO(GPIO_140, LOW),
 	/* USB_HUB_RST_L */
 	PAD_GPO(GPIO_141, HIGH),
 	/* SD_AUX_RESET_L */

src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c

@@ -164,8 +164,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 	/* DEV_BEEP_BCLK */
 	PAD_GPI(GPIO_139, PULL_NONE),
-	/* USI_RESET */
-	PAD_GPO(GPIO_140, HIGH),
+	/* USI_RESET_L */
+	PAD_GPO(GPIO_140, LOW),
 	/* UART1_RXD - FPMCU */
 	PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
 	/* SD_AUX_RESET_L */

src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h

@@ -37,6 +37,8 @@ void variant_devtree_update(void);
 void variant_audio_update(void);
 /* Update bluetooth configuration in devicetree during ramstage. */
 void variant_bluetooth_update(void);
+/* Update touchscreen configuration in devicetree during ramstage. */
+void variant_touchscreen_update(void);
 /* Configure PCIe GPIOs as per variant sequencing requirements. */
 void variant_pcie_gpio_configure(void);
 

src/mainboard/google/zork/variants/baseboard/ramstage_common.c

@@ -6,14 +6,16 @@
 #include <device/device.h>
 #include <drivers/amd/i2s_machine_dev/chip.h>
 #include <drivers/i2c/generic/chip.h>
+#include <drivers/i2c/hid/chip.h>
 #include <drivers/usb/acpi/chip.h>
 #include <ec/google/chromeec/ec.h>
 #include <soc/gpio.h>
+#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 
 extern struct chip_operations drivers_amd_i2s_machine_dev_ops;
 extern struct chip_operations drivers_i2c_generic_ops;
-
+extern struct chip_operations drivers_i2c_hid_ops;
 
 static void update_hp_int_odl(void)
 {
@@ -202,3 +204,52 @@ void variant_bluetooth_update(void)
 
 	baseboard_remove_bluetooth_reset_gpio();
 }
+
+void variant_touchscreen_update(void)
+{
+	DEVTREE_CONST struct device *mmio_dev = NULL;
+	struct device *child = NULL;
+
+	/*
+	 * By default, devicetree/overridetree entries for touchscreen device are configured to
+	 * match v3.6 of reference schematics. So, if the board is using v3.6+ schematics, no
+	 * additional work is required here. For maintaining support for pre-v3.6 boards, rest
+	 * of the code in this function finds all entries that correspond to touchscreen
+	 * devices (identified by reset_gpio being set to GPIO_140) and updates them as per
+	 * pre-v3.6 version of schematics:
+	 * 1. reset_gpio is marked as active high.
+	 */
+	if (variant_uses_v3_6_schematics())
+		return;
+
+	while (1) {
+		mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO);
+		if (mmio_dev == NULL)
+			break;
+		if (mmio_dev->path.mmio.addr == APU_I2C2_BASE)
+			break;
+	}
+
+	if (mmio_dev == NULL)
+		return;
+
+	while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
+		struct drivers_i2c_generic_config *cfg;
+
+		if (child->chip_ops == &drivers_i2c_generic_ops) {
+			cfg = config_of(child);
+		} else if (child->chip_ops == &drivers_i2c_hid_ops) {
+			struct drivers_i2c_hid_config *hid_cfg;
+			hid_cfg = config_of(child);
+			cfg = &hid_cfg->generic;
+		} else {
+			continue;
+		}
+
+		/* If reset_gpio is set to GPIO_140, assume that this is touchscreen device. */
+		if (cfg->reset_gpio.pins[0] != GPIO_140)
+			continue;
+
+		cfg->reset_gpio.active_low = 0;
+	}
+}

src/mainboard/google/zork/variants/berknip/gpio.c

@@ -22,6 +22,13 @@ static const struct soc_amd_gpio berknip_bid1_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
+};
+
+static const struct soc_amd_gpio berknip_bid2_gpio_set_stage_ram[] = {
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
@@ -39,6 +46,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 	if (board_version <= 1) {
 		*size = ARRAY_SIZE(berknip_bid1_gpio_set_stage_ram);
 		return berknip_bid1_gpio_set_stage_ram;
+	} else if (board_version <= 2) {
+		*size = ARRAY_SIZE(berknip_bid2_gpio_set_stage_ram);
+		return berknip_bid2_gpio_set_stage_ram;
 	}
 
 	*size = 0;

src/mainboard/google/zork/variants/dalboz/gpio.c

@@ -15,6 +15,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
 	PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE),
 	/* EN_PWR_TOUCHPAD_PS2 */
 	PAD_GPO(GPIO_67, HIGH),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 	/* Unused */
 	PAD_NC(GPIO_143),
 };
@@ -24,6 +26,8 @@ static const struct soc_amd_gpio bid_2_gpio_set_stage_ram[] = {
 	PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC
 	/* EN_PWR_TOUCHPAD_PS2 */
 	PAD_GPO(GPIO_67, HIGH),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)

src/mainboard/google/zork/variants/dalboz/overridetree.cb

@@ -48,7 +48,7 @@ chip soc/amd/picasso
 			register "desc" = ""Raydium Touchscreen""
 			register "probed" = "1"
 			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
-			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			# 32ms: Rise time of the reset line
 			# 20ms: Firmware ready time
 			register "reset_delay_ms" = "32 + 20"
@@ -61,7 +61,7 @@ chip soc/amd/picasso
 			register "desc" = ""ELAN Touchscreen""
 			register "probed" = "1"
 			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
-			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "reset_delay_ms" = "20"
 			register "has_power_resource" = "1"
 			device i2c 10 on end
@@ -71,7 +71,7 @@ chip soc/amd/picasso
 			register "generic.desc" = ""Synaptics Touchscreen""
 			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
 			register "generic.probed" = "1"
-			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "generic.reset_delay_ms" = "45"
 			register "generic.has_power_resource" = "1"
 			register "generic.disable_gpio_export_in_crs" = "1"
@@ -83,7 +83,7 @@ chip soc/amd/picasso
 			register "generic.desc" = ""Goodix Touchscreen""
 			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
 			register "generic.probed" = "1"
-			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "generic.reset_delay_ms" = "120"
 			register "generic.reset_off_delay_ms" = "1"
 			register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)"

src/mainboard/google/zork/variants/dirinboz/Makefile.inc

@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 subdirs-y += ../baseboard/spd
+
+ramstage-y += gpio.c

src/mainboard/google/zork/variants/dirinboz/gpio.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+	uint32_t board_version;
+
+	/*
+	 * If board version cannot be read, assume that this is an older revision of the board
+	 * and so apply overrides. If board version is provided by the EC, then apply overrides
+	 * if version < 2.
+	 */
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
+		return bid_1_gpio_set_stage_ram;
+	}
+
+	*size = 0;
+	return NULL;
+}

src/mainboard/google/zork/variants/ezkinil/gpio.c

@@ -22,6 +22,8 @@ static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = {
@@ -37,6 +39,8 @@ static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = {
 	PAD_NC(GPIO_69),
 	/* MST_GPIO_2 (Fw Update HDMI hub) Change NC */
 	PAD_NC(GPIO_86),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = {
@@ -44,6 +48,8 @@ static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = {
 	PAD_NC(GPIO_11),
 	/* FPMCU_BOOT0 Change NC */
 	PAD_NC(GPIO_69),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)

src/mainboard/google/zork/variants/morphius/gpio.c

@@ -24,6 +24,8 @@ static const struct soc_amd_gpio morphius_bid1_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = {
@@ -41,6 +43,13 @@ static const struct soc_amd_gpio morphius_bid2_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
+};
+
+static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = {
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
@@ -61,6 +70,9 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 	} else if (board_version <= 2) {
 		*size = ARRAY_SIZE(morphius_bid2_gpio_set_stage_ram);
 		return morphius_bid2_gpio_set_stage_ram;
+	} else if (board_version <= 3) {
+		*size = ARRAY_SIZE(morphius_bid3_gpio_set_stage_ram);
+		return morphius_bid3_gpio_set_stage_ram;
 	}
 
 	*size = 0;

src/mainboard/google/zork/variants/trembyle/gpio.c

@@ -24,6 +24,8 @@ static const struct soc_amd_gpio trembyle_bid1_bid2_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = {
@@ -41,6 +43,8 @@ static const struct soc_amd_gpio trembyle_bid3_gpio_set_stage_ram[] = {
 	PAD_GPI(GPIO_86, PULL_NONE),
 	/* MST_GPIO_3 (Fw Update HDMI hub) */
 	PAD_GPI(GPIO_90, PULL_NONE),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 };
 
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)

src/mainboard/google/zork/variants/trembyle/overridetree.cb

@@ -71,7 +71,7 @@ chip soc/amd/picasso
 			register "desc" = ""Raydium Touchscreen""
 			register "probed" = "1"
 			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
-			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			# 32ms: Rise time of the reset line
 			# 20ms: Firmware ready time
 			register "reset_delay_ms" = "32 + 20"
@@ -84,7 +84,7 @@ chip soc/amd/picasso
 			register "desc" = ""ELAN Touchscreen""
 			register "probed" = "1"
 			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
-			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"
 			register "reset_delay_ms" = "20"
 			register "has_power_resource" = "1"
 			device i2c 10 on end

src/mainboard/google/zork/variants/vilboz/Makefile.inc

@@ -3,3 +3,4 @@
 subdirs-y += ./spd
 
 ramstage-y += variant.c
+ramstage-y += gpio.c

src/mainboard/google/zork/variants/vilboz/gpio.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+	uint32_t board_version;
+
+	/*
+	 * If board version cannot be read, assume that this is an older revision of the board
+	 * and so apply overrides. If board version is provided by the EC, then apply overrides
+	 * if version < 2.
+	 */
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
+		return bid_1_gpio_set_stage_ram;
+	}
+
+	*size = 0;
+	return NULL;
+}

src/mainboard/google/zork/variants/woomax/gpio.c

@@ -18,6 +18,8 @@ static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = {
 	PAD_NC(GPIO_69),
 	/* RAM_ID_4  */
 	PAD_NC(GPIO_84),
+	/* USI_RESET */
+	PAD_GPO(GPIO_140, HIGH),
 	/* GPIO_141 NC */
 	PAD_NC(GPIO_141),
 	/* GPIO_143 NC */