soc/intel/common: Move support to log XHCI wake events
The policy to identify and log the XHCI wake events is similar between skylake and apollolake. Hence move the similar parts to a common location. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13 Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian
Patrick Georgi
parent
e2ac5b7a36
commit
cc7cdb19b1
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@ -16,6 +16,34 @@
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#ifndef SOC_INTEL_COMMON_BLOCK_XHCI_H
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#define SOC_INTEL_COMMON_BLOCK_XHCI_H
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#include <device/device.h>
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/**
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* struct xhci_usb_info - Data containing number of USB ports & offset.
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* @usb2_port_status_reg: Offset to USB2 port status register.
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* @num_usb2_ports: Number of USB2 ports.
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* @usb3_port_status_reg: Offset to USB3 port status register.
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* @num_usb3_ports: Number of USB3 ports.
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*/
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struct xhci_usb_info {
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uint32_t usb2_port_status_reg;
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uint32_t num_usb2_ports;
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uint32_t usb3_port_status_reg;
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uint32_t num_usb3_ports;
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};
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/**
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* pch_xhci_update_wake_event() - Identify and log XHCI wake events.
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* @info: Information about number of USB ports and their status reg offset.
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*
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* This function goes through individual USB port status registers within the
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* XHCI block and identifies if any of those USB ports triggered a wake-up and
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* log information about those ports to the event log.
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*
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* Return: True if any port is identified as a wake source, false if none.
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*/
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bool pch_xhci_update_wake_event(const struct xhci_usb_info *info);
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void soc_xhci_init(struct device *dev);
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#endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */
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@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_XHCI
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bool
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help
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Intel Processor common XHCI support
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config SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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bool
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default n
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depends on SOC_INTEL_COMMON_BLOCK_XHCI
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help
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Set this option to identify if XHCI caused a wake up and log that
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information into the event log.
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@ -1 +1,4 @@
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI) += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c
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smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c
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@ -0,0 +1,155 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <elog.h>
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#include <intelblocks/xhci.h>
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#include <soc/pci_devs.h>
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#include <stdint.h>
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/* Wake on disconnect enable */
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#define XHCI_STATUS_WDE (1 << 26)
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/* Wake on connect enable */
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#define XHCI_STATUS_WCE (1 << 25)
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/* Port link status change */
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#define XHCI_STATUS_PLC (1 << 22)
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/* Connect status change */
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#define XHCI_STATUS_CSC (1 << 17)
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/* Port link status */
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#define XHCI_STATUS_PLS_SHIFT (5)
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#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT)
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#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
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static bool pch_xhci_csc_set(uint32_t port_status)
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{
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return !!(port_status & XHCI_STATUS_CSC);
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}
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static bool pch_xhci_wake_capable(uint32_t port_status)
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{
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return !!((port_status & XHCI_STATUS_WCE) |
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(port_status & XHCI_STATUS_WDE));
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}
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static bool pch_xhci_plc_set(uint32_t port_status)
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{
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return !!(port_status & XHCI_STATUS_PLC);
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}
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static bool pch_xhci_resume(uint32_t port_status)
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{
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return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
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}
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/*
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* Check if a particular USB port caused wake by:
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* 1. Change in connect/disconnect status (if enabled)
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* 2. USB device activity
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*
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* Params:
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* base : MMIO address of first port.
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* num : Number of ports.
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* event : Event that needs to be added in case wake source is found.
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*
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* Return value:
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* true : Wake source was found.
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* false : Wake source was not found.
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*/
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static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
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{
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uint32_t i, port_status;
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bool found = false;
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for (i = 0; i < num; i++, base += 0x10) {
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/* Read port status and control register for the port. */
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port_status = read32((void *)base);
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/* Ensure that the status is not all 1s. */
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if (port_status == 0xffffffff)
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continue;
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/*
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* Check if CSC bit is set and port is capable of wake on
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* connect/disconnect to identify if the port caused wake
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* event for usb attach/detach.
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*/
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if (pch_xhci_csc_set(port_status) &&
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pch_xhci_wake_capable(port_status)) {
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elog_add_event_wake(event, i + 1);
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found = true;
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continue;
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}
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/*
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* Check if PLC is set and PLS indicates resume to identify if
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* the port caused wake event for usb activity.
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*/
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if (pch_xhci_plc_set(port_status) &&
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pch_xhci_resume(port_status)) {
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elog_add_event_wake(event, i + 1);
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found = true;
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}
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}
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return found;
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}
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/*
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* Update elog event and instance depending upon the USB2 port that caused
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* the wake event.
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*
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* Return value:
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* true = Indicates that USB2 wake event was found.
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* false = Indicates that USB2 wake event was not found.
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*/
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static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base,
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const struct xhci_usb_info *info)
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{
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return pch_xhci_port_wake_check(mmio_base + info->usb2_port_status_reg,
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info->num_usb2_ports,
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ELOG_WAKE_SOURCE_PME_XHCI_USB_2);
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}
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/*
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* Update elog event and instance depending upon the USB3 port that caused
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* the wake event.
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*
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* Return value:
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* true = Indicates that USB3 wake event was found.
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* false = Indicates that USB3 wake event was not found.
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*/
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static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base,
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const struct xhci_usb_info *info)
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{
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return pch_xhci_port_wake_check(mmio_base + info->usb3_port_status_reg,
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info->num_usb3_ports,
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ELOG_WAKE_SOURCE_PME_XHCI_USB_3);
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}
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bool pch_xhci_update_wake_event(const struct xhci_usb_info *info)
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{
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uintptr_t mmio_base;
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bool event_found = false;
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mmio_base = ALIGN_DOWN(pci_read_config32(PCH_DEV_XHCI,
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PCI_BASE_ADDRESS_0), 16);
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if (pch_xhci_usb2_update_wake_event(mmio_base, info))
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event_found = true;
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if (pch_xhci_usb3_update_wake_event(mmio_base, info))
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event_found = true;
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return event_found;
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}
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@ -66,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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@ -22,6 +22,7 @@
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#include <stdint.h>
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#include <elog.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/xhci.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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@ -42,142 +43,13 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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#define XHCI_USB3_PORT_STATUS_REG 0x540
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#define XHCI_USB2_PORT_NUM 10
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#define XHCI_USB3_PORT_NUM 6
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/* Wake on disconnect enable */
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#define XHCI_STATUS_WDE (1 << 26)
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/* Wake on connect enable */
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#define XHCI_STATUS_WCE (1 << 25)
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/* Port link status change */
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#define XHCI_STATUS_PLC (1 << 22)
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/* Connect status change */
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#define XHCI_STATUS_CSC (1 << 17)
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/* Port link status */
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#define XHCI_STATUS_PLS_SHIFT (5)
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#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT)
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#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
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static bool pch_xhci_csc_set(uint32_t port_status)
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{
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return !!(port_status & XHCI_STATUS_CSC);
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}
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static bool pch_xhci_wake_capable(uint32_t port_status)
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{
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return !!((port_status & XHCI_STATUS_WCE) |
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(port_status & XHCI_STATUS_WDE));
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}
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static bool pch_xhci_plc_set(uint32_t port_status)
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{
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return !!(port_status & XHCI_STATUS_PLC);
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}
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static bool pch_xhci_resume(uint32_t port_status)
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{
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return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
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}
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/*
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* Check if a particular USB port caused wake by:
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* 1. Change in connect/disconnect status (if enabled)
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* 2. USB device activity
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*
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* Params:
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* base : MMIO address of first port.
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* num : Number of ports.
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* event : Event that needs to be added in case wake source is found.
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*
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* Return value:
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* true : Wake source was found.
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* false : Wake source was not found.
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*/
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static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num,
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uint32_t event)
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{
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uint8_t i;
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uint32_t port_status;
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bool found = false;
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for (i = 0; i < num; i++, base += 0x10) {
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/* Read port status and control register for the port. */
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port_status = read32((void *)base);
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/* Ensure that the status is not all 1s. */
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if (port_status == 0xffffffff)
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continue;
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/*
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* Check if CSC bit is set and port is capable of wake on
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* connect/disconnect to identify if the port caused wake
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* event for usb attach/detach.
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*/
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if (pch_xhci_csc_set(port_status) &&
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pch_xhci_wake_capable(port_status)) {
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elog_add_event_wake(event, i + 1);
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found = true;
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continue;
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}
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/*
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* Check if PLC is set and PLS indicates resume to identify if
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* the port caused wake event for usb activity.
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*/
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if (pch_xhci_plc_set(port_status) &&
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pch_xhci_resume(port_status)) {
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elog_add_event_wake(event, i + 1);
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found = true;
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}
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}
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return found;
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}
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/*
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* Update elog event and instance depending upon the USB2 port that caused
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* the wake event.
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*
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* Return value:
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* true = Indicates that USB2 wake event was found.
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* false = Indicates that USB2 wake event was not found.
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*/
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static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base)
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{
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return pch_xhci_port_wake_check(mmio_base + XHCI_USB2_PORT_STATUS_REG,
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XHCI_USB2_PORT_NUM,
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ELOG_WAKE_SOURCE_PME_XHCI_USB_2);
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}
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/*
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* Update elog event and instance depending upon the USB3 port that caused
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* the wake event.
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*
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* Return value:
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* true = Indicates that USB3 wake event was found.
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* false = Indicates that USB3 wake event was not found.
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*/
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static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base)
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{
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return pch_xhci_port_wake_check(mmio_base + XHCI_USB3_PORT_STATUS_REG,
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XHCI_USB3_PORT_NUM,
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ELOG_WAKE_SOURCE_PME_XHCI_USB_3);
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}
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#ifdef __SIMPLE_DEVICE__
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static bool pch_xhci_update_wake_event(pci_devfn_t dev)
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#else
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static bool pch_xhci_update_wake_event(struct device *dev)
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#endif
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{
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uintptr_t mmio_base;
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bool event_found = false;
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mmio_base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
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if (pch_xhci_usb2_update_wake_event(mmio_base))
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event_found = true;
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if (pch_xhci_usb3_update_wake_event(mmio_base))
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event_found = true;
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return event_found;
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}
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static const struct xhci_usb_info usb_info = {
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.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
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.num_usb2_ports = XHCI_USB2_PORT_NUM,
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.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
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.num_usb3_ports = XHCI_USB3_PORT_NUM,
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};
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struct pme_status_info {
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#ifdef __SIMPLE_DEVICE__
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@ -203,7 +75,8 @@ static void pch_log_add_elog_event(const struct pme_status_info *info,
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* If wake source is XHCI, check for detailed wake source events on
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* USB2/3 ports.
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*/
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if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(dev))
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if ((info->dev == PCH_DEV_XHCI) &&
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pch_xhci_update_wake_event(&usb_info))
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return;
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elog_add_event_wake(info->elog_event, 0);
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@ -251,7 +124,7 @@ static void pch_log_pme_internal_wake_source(void)
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* PME_STS_BIT in controller register.
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*/
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if (!dev_found)
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dev_found = pch_xhci_update_wake_event(PCH_DEV_XHCI);
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dev_found = pch_xhci_update_wake_event(&usb_info);
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if (!dev_found)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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