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soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off 

When one of the General-Purpose PCIe bridges is not used, it doesn't
show up on the PCI bus at all, so coreboot notes it as an issue in the
devicetree. This happens even if the device is marked as off.
To solve this, we're marking the GPP bridge devices in devicetree as
hidden, so they'll only show up in devicetree if they're actually used
on a mainboard.

BUG=b:277997811
TEST=Build

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2023-04-19 13:40:06 -06:00 committed by Felix Held
parent c9ce5f6ec8
commit cc827d9aab
1 changed files with 10 additions and 10 deletions
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20
src/soc/amd/phoenix/chipset.cb
View File

@ -11,19 +11,19 @@ chip soc/amd/phoenix
device pci 01.0 on end # Dummy Host Bridge, do not disable device pci 01.0 on end # Dummy Host Bridge, do not disable
# The PCIe GPP aliases in this SoC match the device and function numbers # The PCIe GPP aliases in this SoC match the device and function numbers
device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end
device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end
device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end
device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end
device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.0 on end # Dummy Host Bridge, do not disable
# The PCIe GPP aliases in this SoC match the device and function numbers # The PCIe GPP aliases in this SoC match the device and function numbers
device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end
device pci 03.0 on end # Dummy Host Bridge, do not disable device pci 03.0 on end # Dummy Host Bridge, do not disable
device pci 03.1 alias usb4_pcie_bridge_0 off end device pci 03.1 alias usb4_pcie_bridge_0 off end