mb/google/brya/var/gladios: Update fw_config STORAGE field

option STORAGE_EMMC 0
option STORAGE_NVME 1

BUG=b:239513596
TEST=FW_NAME=gladios emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Kevin Chiu 2022-12-01 19:58:59 +08:00 committed by Nick Vaccaro
parent fd39a8ef1f
commit cc846838b6
1 changed files with 10 additions and 1 deletions

View File

@ -1,3 +1,10 @@
fw_config
field STORAGE 1 1
option STORAGE_EMMC 0
option STORAGE_NVME 1
end
end
chip soc/intel/alderlake chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
@ -142,7 +149,8 @@ chip soc/intel/alderlake
.clk_src = 0, .clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end probe STORAGE STORAGE_NVME
end #NVMe
device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end device ref tbt_pcie_rp2 off end
@ -201,6 +209,7 @@ chip soc/intel/alderlake
.clk_req = 4, .clk_req = 4,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
}" }"
probe STORAGE STORAGE_EMMC
end #PCIE12 EMMC end #PCIE12 EMMC
device ref gspi1 off end device ref gspi1 off end
device ref pch_espi on device ref pch_espi on