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soc/intel/common/block/lpss: Add provision to set controller power state 

Add function to set the power state of a LPSS controller.
The API implemented can be used to enforce controllers in
active state(D0) during initialization.

BUG=b:135941367

Change-Id: I7540924885350de64caff91d920d6cc234154616
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-07-12 14:34:02 +05:30 committed by Subrata Banik
parent 23c923ba72
commit cc8e992fc3
2 changed files with 28 additions and 0 deletions
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10
src/soc/intel/common/block/include/intelblocks/lpss.h
View File

@ -16,8 +16,15 @@
#ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
#define SOC_INTEL_COMMON_BLOCK_LPSS_H
#include <device/device.h>
#include <stdint.h>
/* D0 and D3 enable config */
enum lpss_pwr_state {
STATE_D0 = 0,
STATE_D3 = 3
};
/* Gets controller out of reset */
void lpss_reset_release(uintptr_t base);
@ -30,4 +37,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
/* Check if controller is in reset. */
bool lpss_is_controller_in_reset(uintptr_t base);
/* Set controller power state to D0 or D3*/
void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state);
#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */

18
src/soc/intel/common/block/lpss/lpss.c
View File

@ -14,6 +14,7 @@
*/
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <intelblocks/lpss.h>
/* Clock register */
@ -39,6 +40,11 @@
/* DMA Software Reset Control */
#define LPSS_DMA_RST_RELEASE (1 << 2)
/* Power management control and status register */
#define PME_CTRL_STATUS 0x84
/* Bit 1:0 Powerstate, controls D0 and D3 state */
#define POWER_STATE_MASK 3
bool lpss_is_controller_in_reset(uintptr_t base)
{
uint8_t *addr = (void *)base;
@ -69,3 +75,15 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
write32(addr, clk_sel);
}
/* Set controller power state to D0 or D3 */
void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state)
{
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t lpss_dev = dev->path.pci.devfn;
#else
const struct device *lpss_dev = dev;
#endif
pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state);
}