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mb/intel/skylake/devicetree: Use comma separated list for arrays 

In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.

While on it, remove superfluous comments related to modified lines.

Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2023-10-23 16:26:20 +02:00 committed by Felix Singer
parent 7a4583a417
commit cc93db9435
6 changed files with 143 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@ -46,31 +46,35 @@ chip soc/intel/skylake
# USB related
register "SsicPortEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{

36
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -74,24 +74,26 @@ chip soc/intel/skylake
# RP10, uses CLK SRC 4
register "PcieRpClkSrcNumber[9]" = "4"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port
register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port
register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */
[5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
}"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN

49
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@ -1,9 +1,10 @@
chip soc/intel/skylake
# SATA port 0
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
}"
# Enable deep Sx states
register "deep_s5_enable_ac" = "1"
@ -112,26 +113,28 @@ chip soc/intel/skylake
# RP 9 uses CLK SRC 1#
register "PcieRpClkSrcNumber[8]" = "1"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port
register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MAX(OC1), /* Type-A Port */
[5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */
[8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
[11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */
}"
# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
[3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */
[4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

52
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -95,31 +95,35 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "6"
register "PcieRpClkReqNumber[16]" = "7"
register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)" # Front panel
register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)" # Back panel
register "usb2_ports[3]" = "USB2_PORT_MAX(OC4)" # Back panel
register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Back panel-1
register "usb2_ports[5]" = "USB2_PORT_MAX(OC1)" # Back panel
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # Front panel
register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # M.2 BT
register "usb2_ports[9]" = "USB2_PORT_MAX(OC2)" # Front panel
register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel-1
register "usb2_ports[12]" = "USB2_PORT_MAX(OC3)" # Back panel
register "usb2_ports[13]" = "USB2_PORT_MAX(OC_SKIP)" # Back panel
register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC2), /* Type-C Port */
[1] = USB2_PORT_MAX(OC5), /* Front panel */
[2] = USB2_PORT_MAX(OC4), /* Back panel */
[3] = USB2_PORT_MAX(OC4), /* Back panel */
[4] = USB2_PORT_MAX(OC1), /* Back panel-1 */
[5] = USB2_PORT_MAX(OC1), /* Back panel */
[6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */
[8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */
[9] = USB2_PORT_MAX(OC2), /* Front panel */
[10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
[11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */
[12] = USB2_PORT_MAX(OC3), /* Back panel */
[13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */
}"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Back panel
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # Back panel-2
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Front Panel
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Front Panel
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC3)" # Back panel
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LAN
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */
[1] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[2] = USB3_PORT_DEFAULT(OC1), /* Back panel */
[3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */
[4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */
[8] = USB3_PORT_DEFAULT(OC3), /* Back panel */
[9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */
}"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN

24
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -117,17 +117,21 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), /* Type-C Port 1 */
[1] = USB2_PORT_TYPE_C(OC1), /* Type-C Port 2 */
[2] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
[4] = USB2_PORT_MID(OC2), /* Type-A Port (card) */
[6] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
[8] = USB2_PORT_LONG(OC3), /* Type-A Port (board) */
}"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* Type-C Port 1 */
[1] = USB3_PORT_DEFAULT(OC1), /* Type-C Port 2 */
[2] = USB3_PORT_DEFAULT(OC2), /* Type-A Port (card) */
[3] = USB3_PORT_DEFAULT(OC3), /* Type-A Port (board) */
}"
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V

52
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -126,31 +126,35 @@ chip soc/intel/skylake
# USB related
register "SsicPortEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */
[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
[5] = USB2_PORT_MID(OC0), /* Front Panel */
[6] = USB2_PORT_MID(OC0), /* Front Panel */
[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
}"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
}"
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V