soc/amd/cezanne/Kconfig: select missing SSE2 option

This will set the corresponding enable bit in CR4 in bootblock_crt0.S

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-01-23 00:18:08 +01:00
parent f09221c033
commit cc975c5c65
1 changed files with 1 additions and 0 deletions

View File

@ -28,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
select SSE2
select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS