mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus

Follow the latest HW schematic change.

BUG=b:208556921
TEST=build pass

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eric Lai 2021-12-01 17:00:27 +08:00 committed by Tim Wawrzynczak
parent effe39b1f6
commit cca657f898
3 changed files with 41 additions and 14 deletions

View File

@ -79,7 +79,7 @@ config DRIVER_TPM_I2C_BUS
default 0x3 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX
default 0x1 if BOARD_GOOGLE_KANO default 0x1 if BOARD_GOOGLE_KANO
default 0x3 if BOARD_GOOGLE_TAEKO default 0x3 if BOARD_GOOGLE_TAEKO
default 0x3 if BOARD_GOOGLE_FELWINTER default 0x1 if BOARD_GOOGLE_FELWINTER
default 0x3 if BOARD_GOOGLE_ANAHERA default 0x3 if BOARD_GOOGLE_ANAHERA
default 0x3 if BOARD_GOOGLE_VELL default 0x3 if BOARD_GOOGLE_VELL

View File

@ -114,10 +114,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP), PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP), PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* D18 : UART1_TXD ==> SD_PE_RST_L */ /* D18 : UART1_TXD ==> SD_PE_RST_L */

View File

@ -40,6 +40,33 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}" }"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C3 | Touchscreen |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on device domain 0 on
device ref dtt on device ref dtt on
chip drivers/intel/dptf chip drivers/intel/dptf
@ -206,6 +233,13 @@ chip soc/intel/alderlake
end end
end #I2C0 end #I2C0
device ref i2c1 on device ref i2c1 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
device i2c 50 on end
end
end #I2C1
device ref i2c3 on
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""ELAN9050"" register "generic.hid" = ""ELAN9050""
register "generic.desc" = ""ELAN Touchscreen"" register "generic.desc" = ""ELAN Touchscreen""
@ -237,14 +271,7 @@ chip soc/intel/alderlake
register "key.label" = ""pen_eject"" register "key.label" = ""pen_eject""
device generic 0 on end device generic 0 on end
end end
end end #I2C3
device ref i2c3 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
device i2c 50 on end
end
end
device ref i2c5 on device ref i2c5 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""ELAN0000"" register "hid" = ""ELAN0000""
@ -254,7 +281,7 @@ chip soc/intel/alderlake
register "probed" = "1" register "probed" = "1"
device i2c 15 on end device i2c 15 on end
end end
end end #I2C5
device ref hda on device ref hda on
chip drivers/generic/max98357a chip drivers/generic/max98357a
register "hid" = ""MX98360A"" register "hid" = ""MX98360A""