Adds VOID to empty parameter lists to get rid of some build warnings.

This change modifies a collection of files by adding the VOID parameter
to empty parameter lists to cut down on the number of warnings produced
when compiling the AMD Agesa code.  This should cut down the number of
warnings by about 1100 each for rom- and ramstage.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h

@@ -151,14 +151,14 @@ GetCurrentNodeNum (
  *
  */
 UINT32
-GetPlatformNumberOfSockets ();
+GetPlatformNumberOfSockets (VOID);
 
 /**
  * Get the number of Modules to check presence in each Processor.
  *
  */
 UINT32
-GetPlatformNumberOfModules ();
+GetPlatformNumberOfModules (VOID);
 
 BOOLEAN
 IsProcessorPresent (

src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c

@@ -70,7 +70,7 @@ RDATA_GROUP (G1_PEICC)
 * @retval TRUE  Default case, no special action
 */
 BOOLEAN
-CommonReturnTrue ()
+CommonReturnTrue (VOID)
 {
   return TRUE;
 }
@@ -83,7 +83,7 @@ CommonReturnTrue ()
 * @retval FALSE  Default case, no special action
 */
 BOOLEAN
-CommonReturnFalse ()
+CommonReturnFalse (VOID)
 {
   return FALSE;
 }
@@ -96,7 +96,7 @@ CommonReturnFalse ()
  * @retval zero    None, or only case zero.
  */
 UINT8
-CommonReturnZero8 ()
+CommonReturnZero8 (VOID)
 {
   return 0;
 }
@@ -109,7 +109,7 @@ CommonReturnZero8 ()
  * @retval zero    None, or only case zero.
  */
 UINT32
-CommonReturnZero32 ()
+CommonReturnZero32 (VOID)
 {
   return 0;
 }
@@ -122,7 +122,7 @@ CommonReturnZero32 ()
  * @retval zero    None, or only case zero.
  */
 UINT64
-CommonReturnZero64 ()
+CommonReturnZero64 (VOID)
 {
   return 0;
 }
@@ -134,7 +134,7 @@ CommonReturnZero64 ()
  * @retval NULL    pointer to nothing
  */
 VOID *
-CommonReturnNULL ()
+CommonReturnNULL (VOID)
 {
   return NULL;
 }
@@ -146,7 +146,7 @@ CommonReturnNULL ()
 * @retval AGESA_SUCCESS Success.
 */
 AGESA_STATUS
-CommonReturnAgesaSuccess ()
+CommonReturnAgesaSuccess (VOID)
 {
   return AGESA_SUCCESS;
 }
@@ -158,7 +158,7 @@ CommonReturnAgesaSuccess ()
  *
  */
 VOID
-CommonVoid ()
+CommonVoid (VOID)
 {
 }
 
@@ -168,7 +168,7 @@ CommonVoid ()
  *
  */
 VOID
-CommonAssert ()
+CommonAssert (VOID)
 {
   ASSERT (FALSE);
 }

src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c

@@ -115,6 +115,7 @@ NbFmClumpUnitID (
 
 FUSE_TABLE*
 NbFmGetFuseTranslationTable (
+  VOID
   )
 {
   return  &FuseTable;

src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h

@@ -86,6 +86,7 @@ NbFmClumpUnitID (
 
 FUSE_TABLE*
 NbFmGetFuseTranslationTable (
+  VOID
   );
 
 VOID

src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c

@@ -89,7 +89,7 @@ RDATA_GROUP (G1_PEICC)
  */
 
 VOID
-memDefRet ()
+memDefRet (VOID)
 {
 }
 
@@ -100,7 +100,7 @@ memDefRet ()
  *
  */
 BOOLEAN
-memDefTrue ()
+memDefTrue (VOID)
 {
   return TRUE;
 }
@@ -112,7 +112,7 @@ memDefTrue ()
  *
  */
 BOOLEAN
-memDefFalse ()
+memDefFalse (VOID)
 {
   return FALSE;
 }
@@ -137,7 +137,7 @@ MemMFlowDef (
  *
  */
 AGESA_STATUS
-memDefRetSuccess ()
+memDefRetSuccess (VOID)
 {
   return AGESA_SUCCESS;
 }

src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c

@@ -150,11 +150,11 @@ MemTSkipChipSelPass2Byte (
 
 UINT8
 STATIC
-MemTMaxByteLanesByte ();
+MemTMaxByteLanesByte (VOID);
 
 UINT8
 STATIC
-MemTDlyTableWidthByte ();
+MemTDlyTableWidthByte (VOID);
 
 VOID
 STATIC
@@ -689,7 +689,7 @@ MemTSkipChipSelPass2Byte (
 
 UINT8
 STATIC
-MemTMaxByteLanesByte ()
+MemTMaxByteLanesByte (VOID)
 {
   return MAX_BYTELANES;
 }
@@ -704,7 +704,7 @@ MemTMaxByteLanesByte ()
 
 UINT8
 STATIC
-MemTDlyTableWidthByte ()
+MemTDlyTableWidthByte (VOID)
 {
   return MAX_DELAYS;
 }

src/vendorcode/amd/agesa/Proc/Mem/mm.h

@@ -984,10 +984,10 @@ AmdMemInitDataStructDefRecovery (
   );
 
 VOID
-MemRecDefRet ();
+MemRecDefRet (VOID);
 
 BOOLEAN
-MemRecDefTrue ();
+MemRecDefTrue (VOID);
 
 VOID
 SetMemRecError (
@@ -996,7 +996,7 @@ SetMemRecError (
   );
 
 AGESA_STATUS
-memDefRetSuccess ();
+memDefRetSuccess (VOID);
 
 #endif  /* _MM_H_ */
 

src/vendorcode/amd/agesa/Proc/Mem/mn.h

@@ -548,7 +548,7 @@ typedef struct _MEM_NB_BLOCK {
   VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
   UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
   VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
-  UINT32 (*GetSysAddrRec) (); ///< Get system address for training.
+  UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training.
   VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
   VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
   VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
@@ -979,6 +979,7 @@ MemRecNCPUMemRecTypingNb (
 
 UINT32
 MemRecNGetMCTSysAddrNb (
+  VOID
   );
 
 UINT32

src/vendorcode/amd/agesa/Proc/Mem/mt.h

@@ -206,11 +206,11 @@ typedef struct _MEM_TECH_BLOCK {
   VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
   VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
   UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
-  UINT8 (*MaxByteLanes) (); ///< return maximum number of bytelanes.
+  UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes.
   VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
   VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
   BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
-  UINT8 (*DlyTableWidth) (); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
+  UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
   UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
   VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
   VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.

src/vendorcode/amd/agesa/Proc/Mem/mu.h

@@ -230,6 +230,7 @@ GetVarMtrrHiMsk (
 
 VOID
 MemUMFenceInstr (
+  VOID
   );
 
 #endif  /* _MU_H_ */