peppy: Disable audio codec enable GPIO in S3 + S5.

To save power, disable audio codec in S3 + S5.

Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM
binary.

Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60950
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4339
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/mainboard/google/peppy/smihandler.c

@@ -32,6 +32,9 @@
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
 
+/* Codec enable: GPIO45 */
+#define GPIO_PP3300_CODEC_EN 45
+
 int mainboard_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -98,6 +101,8 @@ void mainboard_smi_sleep(u8 slp_typ)
 		if (smm_get_gnvs()->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
+
+		set_gpio(GPIO_PP3300_CODEC_EN, 0);
 		break;
 	case 5:
 		if (smm_get_gnvs()->s5u0 == 0)
@@ -106,6 +111,8 @@ void mainboard_smi_sleep(u8 slp_typ)
 		if (smm_get_gnvs()->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
+
+		set_gpio(GPIO_PP3300_CODEC_EN, 0);
 		break;
 	}
 

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -56,9 +56,11 @@ romstage-y += reset.c early_spi.c rcba.c
 ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
 romstage-y += lp_gpio.c
 ramstage-y += lp_gpio.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
 else
 romstage-y += gpio.c
 ramstage-y += gpio.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
 endif
 
 lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL)

src/southbridge/intel/lynxpoint/gpio.c

@@ -29,7 +29,7 @@
 
 static u16 get_gpio_base(void)
 {
-#ifdef __PRE_RAM__
+#if defined(__PRE_RAM__) || defined(__SMM__)
 	return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
 #else
 	return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),

src/southbridge/intel/lynxpoint/lp_gpio.c

@@ -28,7 +28,7 @@
 
 static u16 get_gpio_base(void)
 {
-#ifdef __PRE_RAM__
+#if defined(__PRE_RAM__) || defined(__SMM__)
 	return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
 #else
 	return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),

src/southbridge/intel/lynxpoint/pch.h

@@ -163,6 +163,21 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
 void disable_all_gpe(void);
 void enable_gpe(u32 mask);
 void disable_gpe(u32 mask);
+/*
+ * get GPIO pin value
+ */
+int get_gpio(int gpio_num);
+/*
+ * Get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+/*
+ * Set GPIO pin value.
+ */
+void set_gpio(int gpio_num, int value);
+/* Return non-zero if gpio is set to native function. 0 otherwise. */
+int gpio_is_native(int gpio_num);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
@@ -194,23 +209,8 @@ int smbus_read_byte(unsigned device, unsigned address);
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 int early_pch_init(const void *gpio_map,
                    const struct rcba_config_instruction *rcba_config);
-#endif
-/*
- * get GPIO pin value
- */
-int get_gpio(int gpio_num);
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned get_gpios(const int *gpio_num_array);
-/*
- * set GPIO pin value
- */
-void set_gpio(int gpio_num, int value);
-/* Return non-zero if gpio is set to native function. 0 otherwise. */
-int gpio_is_native(int gpio_num);
-#endif
+#endif /* !__PRE_RAM__ && !__SMM__ */
+#endif /* __ASSEMBLER__ */
 
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1
@@ -793,4 +793,4 @@ int gpio_is_native(int gpio_num);
 #define SPIBAR_FDATA(n)             (0x3810 + (4 * n)) /* SPI flash data */
 
 #endif /* __ACPI__ */
-#endif				/* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */
+#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */