diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index f444852e54..51c6b52248 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -1438,6 +1438,13 @@ SetupStack:
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 0fbcf77eea..b9cc39fac5 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -1179,6 +1179,13 @@ w64k_here:
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 2399bec91b..46946327ce 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -1158,6 +1158,13 @@ w64k_here:
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 7e12db1d06..6c4ad596e1 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -1153,6 +1153,13 @@ SetupStack:
     0:
     _WRMSR                              #
 
+    # All cores must see BSP stack region that is also used to
+    # communicate global variables before DRAM is up.
+    mov     $AMD_MTRR_FIX64k_00000, %ecx  # MSR:0000_0250
+    _RDMSR
+    or      $0x1e000000, %eax
+    _WRMSR                              #
+
     # Enable MTRR defaults as UC type
     mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
     _RDMSR                              # Read-modify-write the MSR