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mb/google/poppy/variants/nocturne: set nvme to use clk src 3 

Latest nocturne architecture uses clk src 3 for nvme.

BUG=b:111514174
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme
nocturne devices are able to recognize the nvme controller.

Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27536
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2018-07-18 11:19:40 -07:00 committed by Patrick Georgi
parent c430ecec9e
commit ccb62960db
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
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@ -164,13 +164,13 @@ chip soc/intel/skylake
# PcieRpEnable: Enable root port # PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkReqNumber: Uses SRCCLKREQ2#
# PcieRpClkSrcNumber: Uses 2 # PcieRpClkSrcNumber: Uses 3
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpClkSrcNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3"
register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"