soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN

Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.

BRANCH=None
BUG=None
TEST=Built and tested on dedede board

Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar 2020-09-11 18:51:36 +05:30 committed by Patrick Georgi
parent e5655a11d2
commit ccbe5307d8
4 changed files with 3 additions and 8 deletions

View File

@ -155,9 +155,6 @@ chip soc/intel/jasperlake
.tdp_pl2_override = 20, .tdp_pl2_override = 20,
}" }"
# Enable processor thermal control
register "Device4Enable" = "1"
register "tcc_offset" = "10" # TCC of 90C register "tcc_offset" = "10" # TCC of 90C
# chipset_lockdown configuration # chipset_lockdown configuration

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@ -128,9 +128,6 @@ chip soc/intel/jasperlake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# Enable Processor Thermal Control
register "Device4Enable" = "1"
# Add PL1 and PL2 values # Add PL1 and PL2 values
register "power_limits_config" = "{ register "power_limits_config" = "{
.tdp_pl1_override = 6, .tdp_pl1_override = 6,

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@ -142,7 +142,6 @@ struct soc_intel_jasperlake_config {
uint8_t SkipExtGfxScan; uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr; uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot /* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */ * Setting to 0 (default) disables Heci1 and hides the device from OS */

View File

@ -183,7 +183,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (params->ScsSdCardEnabled) if (params->ScsSdCardEnabled)
params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
params->Device4Enable = config->Device4Enable; /* Enable Processor Thermal Control */
dev = pcidev_path_on_root(SA_DEVFN_DPTF);
params->Device4Enable = is_dev_enabled(dev);
/* Set TccActivationOffset */ /* Set TccActivationOffset */
params->TccActivationOffset = config->tcc_offset; params->TccActivationOffset = config->tcc_offset;