From ccc27d2ccad2e016262923ee241b1569a6085118 Mon Sep 17 00:00:00 2001 From: Dmitry Ponamorev Date: Wed, 15 Sep 2021 03:19:15 -0700 Subject: [PATCH] soc/intel/baytrail,denverton_ns: Call setup_lapic() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Similar change was done for soc/intel/braswell in commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1. Signed-off-by: Dmitry Ponamorev Signed-off-by: Kyösti Mälkki Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/baytrail/cpu.c | 3 +++ src/soc/intel/denverton_ns/cpu.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 1dbc3d7751..eb24f7bf8c 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -36,6 +36,9 @@ static void soc_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); + /* Enable the local CPU apics */ + setup_lapic(); + /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 126a1c651f..ef1140b76a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -91,6 +92,9 @@ static void denverton_core_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); + /* Enable the local CPU apics */ + setup_lapic(); + /* Enable speed step. Always ON.*/ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT;