arch/x86: Allow soc/chipset to set linking address
Until recently x86 romstage used to be linked at some default address. The address itself is not meaningful because the code was normally relocated at address calculated during insertion in CBFS. Since some newer SoC run romstage at CAR it became useful to link romstage code at some address in CAR and avoid relocation during build/run time altogether. Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -161,3 +161,13 @@ config COMPILE_IN_DSDT
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config C_ENV_BOOTBLOCK_SIZE
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config C_ENV_BOOTBLOCK_SIZE
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hex
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hex
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default 0x10000
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default 0x10000
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# Default address romstage is to be linked at
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config ROMSTAGE_ADDR
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hex
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default 0x2000000
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# Default address verstage is to be linked at
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config VERSTAGE_ADDR
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hex
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default 0x2000000
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@ -31,14 +31,14 @@ SECTIONS
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#elif ENV_ROMSTAGE
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#elif ENV_ROMSTAGE
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/* The 1M size is not allocated. It's just for basic size checking.
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/* The 1M size is not allocated. It's just for basic size checking.
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* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
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* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
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ROMSTAGE(32M, 1M)
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ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
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/* Pull in the cache-as-ram rules. */
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/* Pull in the cache-as-ram rules. */
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#include "car.ld"
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#include "car.ld"
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#elif ENV_VERSTAGE
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#elif ENV_VERSTAGE
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/* The 1M size is not allocated. It's just for basic size checking.
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/* The 1M size is not allocated. It's just for basic size checking.
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* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
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* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
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VERSTAGE(32M, 1M)
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VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
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/* Pull in the cache-as-ram rules. */
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/* Pull in the cache-as-ram rules. */
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#include "car.ld"
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#include "car.ld"
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