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arch/x86: Allow soc/chipset to set linking address 

Until recently x86 romstage used to be linked at some default
address. The address itself is not meaningful because the code
was normally relocated at address calculated during insertion
in CBFS. Since some newer SoC run romstage at CAR it became
useful to link romstage code at some address in CAR and avoid
relocation during build/run time altogether.

Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Andrey Petrov 2016-02-28 22:04:51 -08:00 committed by Aaron Durbin
parent f8468d43e0
commit ccd300b4b4
2 changed files with 12 additions and 2 deletions
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10
src/arch/x86/Kconfig
View File

@ -161,3 +161,13 @@ config COMPILE_IN_DSDT
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x10000
# Default address romstage is to be linked at
config ROMSTAGE_ADDR
hex
default 0x2000000
# Default address verstage is to be linked at
config VERSTAGE_ADDR
hex
default 0x2000000

4
src/arch/x86/memlayout.ld
View File

@ -31,14 +31,14 @@ SECTIONS
#elif ENV_ROMSTAGE
/* The 1M size is not allocated. It's just for basic size checking.
* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
ROMSTAGE(32M, 1M)
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
/* Pull in the cache-as-ram rules. */
#include "car.ld"
#elif ENV_VERSTAGE
/* The 1M size is not allocated. It's just for basic size checking.
* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
VERSTAGE(32M, 1M)
VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
/* Pull in the cache-as-ram rules. */
#include "car.ld"