GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: Use common PCR module 

This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2017-03-08 17:55:26 +05:30 committed by Martin Roth
parent e7ceae7950
commit ccd8700cac
11 changed files with 106 additions and 135 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/apollolake/Kconfig
View File

@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
# CPU specific options
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select IOAPIC
select PCR_COMMON_IOSF_1_0
select SMP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
@ -91,9 +93,11 @@ config SOC_INTEL_COMMON_RESET
bool
default y
config IOSF_BASE_ADDRESS
hex "MMIO Base Address of sideband bus"
config PCR_BASE_ADDRESS
hex
default 0xd0000000
help
This option allows you to select MMIO Base Address of sideband bus.
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"

17
src/soc/intel/apollolake/acpi/gpio.asl
View File

@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <soc/gpio_defs.h>
#include <soc/pcr_ids.h>
#include "gpiolib.asl"
scope (\_SB) {
@ -39,8 +40,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_N, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
ShiftLeft (PID_GPIO_N, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@ -70,8 +71,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_NW, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
ShiftLeft (PID_GPIO_NW, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@ -101,8 +102,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_W, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
ShiftLeft (PID_GPIO_W, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}
@ -132,8 +133,8 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_SW, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
ShiftLeft (PID_GPIO_SW, PCR_PORTID_SHIFT, Local0)
Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF)
}

4
src/soc/intel/apollolake/acpi/scs.asl
View File

@ -17,8 +17,8 @@ Scope (\_SB.PCI0) {
/* 0xD6- is the port address */
/* 0x600- is the dynamic clock gating control register offset (GENR) */
OperationRegion (SBMM, SystemMemory,
Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
ShiftLeft(0xD6, 16)), 0x0600), 0x18)
Or ( Or (CONFIG_PCR_BASE_ADDRESS,
ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
Field (SBMM, DWordAcc, NoLock, Preserve)
{
GENR, 32,

1
src/soc/intel/apollolake/acpi/southbridge.asl
View File

@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <intelblocks/pcr.h>
#include <soc/gpe.h>
/* Power button. */

14
src/soc/intel/apollolake/bootblock/bootblock.c
View File

@ -18,21 +18,25 @@
#include <bootblock_common.h>
#include <cpu/x86/mtrr.h>
#include <device/pci.h>
#include <intelblocks/pcr.h>
#include <intelblocks/systemagent.h>
#include <lib.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/flash_ctrlr.h>
#include <soc/gpio.h>
#include <soc/iosf.h>
#include <soc/mmap_boot.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
#include <soc/uart.h>
#include <spi-generic.h>
#include <timestamp.h>
#define PCR_RTC_CONF 0x3400
#define PCR_RTC_CONF_UCMOS_EN 0x4
static const struct pad_config tpm_spi_configs[] = {
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
};
@ -45,9 +49,7 @@ static void tpm_enable(void)
static void enable_cmos_upper_bank(void)
{
uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG);
reg |= RTC_CONFIG_UCMOS_ENABLE;
iosf_write(IOSF_RTC_PORT_ID, RTC_CONFIG, reg);
pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
}
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
@ -57,8 +59,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
bootblock_systemagent_early_init();
dev = PCH_DEV_P2SB;
/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
/* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

71
src/soc/intel/apollolake/gpio.c
View File

@ -17,9 +17,10 @@
#include <assert.h>
#include <gpio.h>
#include <intelblocks/pcr.h>
#include <soc/gpio.h>
#include <soc/iosf.h>
#include <soc/itss.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
/* This list must be in order, from highest pad numbers, to lowest pad numbers*/
@ -31,25 +32,25 @@ static const struct pad_community {
const char *grp_name;
} gpio_communities[] = {
{
.port = GPIO_SW,
.port = PID_GPIO_SW,
.first_pad = SW_OFFSET,
.num_gpi_regs = NUM_SW_GPI_REGS,
.gpi_offset = 0,
.grp_name = "GPIO_GPE_SW",
}, {
.port = GPIO_W,
.port = PID_GPIO_W,
.first_pad = W_OFFSET,
.num_gpi_regs = NUM_W_GPI_REGS,
.gpi_offset = NUM_SW_GPI_REGS,
.grp_name = "GPIO_GPE_W",
}, {
.port = GPIO_NW,
.port = PID_GPIO_NW,
.first_pad = NW_OFFSET,
.num_gpi_regs = NUM_NW_GPI_REGS,
.gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
.grp_name = "GPIO_GPE_NW",
}, {
.port = GPIO_N,
.port = PID_GPIO_N,
.first_pad = N_OFFSET,
.num_gpi_regs = NUM_N_GPI_REGS,
.gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
@ -92,7 +93,7 @@ static void gpio_configure_itss(const struct pad_config *cfg,
if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC))
return;
irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t));
irq = pcr_read32(port, pad_cfg_offset + sizeof(uint32_t));
irq &= PAD_CFG1_IRQ_MASK;
if (!irq) {
printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
@ -106,7 +107,6 @@ static void gpio_configure_itss(const struct pad_config *cfg,
static void gpio_configure_owner(const struct pad_config *cfg,
uint16_t port, int pin)
{
uint32_t val;
uint16_t hostsw_reg;
/* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
@ -119,9 +119,7 @@ static void gpio_configure_owner(const struct pad_config *cfg,
* HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
*/
hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t));
val = iosf_read(port, hostsw_reg);
val |= 1 << (pin % 32);
iosf_write(port, hostsw_reg, val);
pcr_or32(port, hostsw_reg, (1 << (pin % 32)));
}
static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
@ -137,15 +135,13 @@ static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
group = pin / GPIO_MAX_NUM_PER_GROUP;
sts_reg = GPI_SMI_STS_OFFSET(group);
value = iosf_read(port, sts_reg);
value = pcr_read32(port, sts_reg);
/* Write back 1 to reset the sts bits */
iosf_write(port, sts_reg, value);
pcr_write32(port, sts_reg, value);
/* Set enable bits */
en_reg = GPI_SMI_EN_OFFSET(group);
value = iosf_read(port, en_reg);
value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP);
iosf_write(port, en_reg, value);
pcr_or32(port, en_reg, (1 << (pin % GPIO_MAX_NUM_PER_GROUP)));
}
void gpio_configure_pad(const struct pad_config *cfg)
@ -162,8 +158,8 @@ void gpio_configure_pad(const struct pad_config *cfg)
dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK)
<< PAD_CFG1_IOSSTATE_SHIFT;
iosf_write(comm->port, config_offset, cfg->config0);
iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);
pcr_write32(comm->port, config_offset, cfg->config0);
pcr_write32(comm->port, config_offset + sizeof(uint32_t), dw1);
gpio_configure_itss(cfg, comm->port, config_offset);
gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad);
@ -186,7 +182,8 @@ void *gpio_dwx_address(const uint16_t pad)
* returns - address of GPIO
*/
const struct pad_community *comm = gpio_get_community(pad);
return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad));
return pcr_reg_address(comm->port,
PAD_CFG_OFFSET(pad - comm->first_pad));
}
void gpio_input_pulldown(gpio_t gpio)
@ -219,21 +216,18 @@ int gpio_get(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num);
uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
reg = iosf_read(comm->port, config_offset);
reg = pcr_read32(comm->port, config_offset);
return !!(reg & PAD_CFG0_RX_STATE);
}
void gpio_set(gpio_t gpio_num, int value)
{
uint32_t reg;
const struct pad_community *comm = gpio_get_community(gpio_num);
uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
reg = iosf_read(comm->port, config_offset);
reg &= ~PAD_CFG0_TX_STATE;
reg |= !!value & PAD_CFG0_TX_STATE;
iosf_write(comm->port, config_offset, reg);
pcr_rmw32(comm->port, config_offset,
~PAD_CFG0_TX_STATE, (!!value & PAD_CFG0_TX_STATE));
}
const char *gpio_acpi_path(gpio_t gpio_num)
@ -241,13 +235,13 @@ const char *gpio_acpi_path(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num);
switch (comm->port) {
case GPIO_N:
case PID_GPIO_N:
return "\\_SB.GPO0";
case GPIO_NW:
case PID_GPIO_NW:
return "\\_SB.GPO1";
case GPIO_W:
case PID_GPIO_W:
return "\\_SB.GPO2";
case GPIO_SW:
case PID_GPIO_SW:
return "\\_SB.GPO3";
}
@ -259,13 +253,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num);
switch (comm->port) {
case GPIO_N:
case PID_GPIO_N:
return PAD_N(gpio_num);
case GPIO_NW:
case PID_GPIO_NW:
return PAD_NW(gpio_num);
case GPIO_W:
case PID_GPIO_W:
return PAD_W(gpio_num);
case GPIO_SW:
case PID_GPIO_SW:
return PAD_SW(gpio_num);
}
@ -315,13 +309,13 @@ void gpi_clear_get_smi_status(struct gpi_status *sts)
num_groups = comm->num_gpi_regs;
index = comm->gpi_offset;
for (group = 0; group < num_groups; group++, index++) {
sts_value = iosf_read(gpio_communities[i].port,
sts_value = pcr_read32(gpio_communities[i].port,
GPI_SMI_STS_OFFSET(group));
en_value = iosf_read(gpio_communities[i].port,
en_value = pcr_read32(gpio_communities[i].port,
GPI_SMI_EN_OFFSET(group));
sts->grp[index] = sts_value & en_value;
/* Clear the set status bits. */
iosf_write(gpio_communities[i].port,
pcr_write32(gpio_communities[i].port,
GPI_SMI_STS_OFFSET(group), sts->grp[index]);
}
}
@ -376,7 +370,6 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
int i;
uint32_t misccfg_mask;
uint32_t misccfg_value;
uint32_t value;
int ret;
/* Get the group here for community specific MISCCFG register.
@ -412,9 +405,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) {
const struct pad_community *comm = &gpio_communities[i];
value = iosf_read(comm->port, GPIO_MISCCFG);
value &= misccfg_mask;
value |= misccfg_value;
iosf_write(comm->port, GPIO_MISCCFG, value);
pcr_rmw32(comm->port, GPIO_MISCCFG,
misccfg_mask, misccfg_value);
}
}

7
src/soc/intel/apollolake/include/soc/gpio_defs.h
View File

@ -129,13 +129,6 @@
#define PAD_CFG_BASE 0x500
#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
/* IOSF port numbers for GPIO comminuties*/
#define GPIO_SW 0xc0
#define GPIO_S 0xc2
#define GPIO_NW 0xc4
#define GPIO_N 0xc5
#define GPIO_W 0xc7
#define GPI_SMI_STS_0 0x140
#define GPI_SMI_EN_0 0x150
#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4))

2
src/soc/intel/apollolake/include/soc/iomap.h
View File

@ -20,7 +20,7 @@
#include <commonlib/helpers.h>
#define P2SB_BAR CONFIG_IOSF_BASE_ADDRESS
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB)
#define MCH_BASE_ADDR 0xfed10000
#define MCH_BASE_SIZE (32 * KiB)

42
src/soc/intel/apollolake/include/soc/iosf.h
View File

@ -1,42 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_APOLLOLAKE_IOSF_H_
#define _SOC_APOLLOLAKE_IOSF_H_
#include <arch/io.h>
#define IOSF_RTC_PORT_ID 0xD1
#define RTC_CONFIG 0x3400
#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
static inline void *iosf_address(uint16_t port, uint16_t reg)
{
uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
return (void *)addr;
}
static inline void iosf_write(uint16_t port, uint16_t reg, uint32_t val)
{
write32(iosf_address(port, reg), val);
}
static inline uint32_t iosf_read(uint16_t port, uint16_t reg)
{
return read32(iosf_address(port, reg));
}
#endif /* _SOC_APOLLOLAKE_IOSF_H_ */

30
src/soc/intel/apollolake/include/soc/pcr_ids.h Normal file
View File

@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_APL_PCR_H
#define SOC_INTEL_APL_PCR_H
/*
* Port ids.
*/
#define PID_GPIO_SW 0xC0
#define PID_GPIO_S 0xC2
#define PID_GPIO_NW 0xC4
#define PID_GPIO_N 0xC5
#define PID_GPIO_W 0xC7
#define PID_ITSS 0xD0
#define PID_RTC 0xD1
#endif /* SOC_INTEL_APL_PCR_H */

45
src/soc/intel/apollolake/itss.c
View File

@ -15,34 +15,29 @@
#include <commonlib/helpers.h>
#include <console/console.h>
#include <intelblocks/pcr.h>
#include <stdint.h>
#include <soc/iosf.h>
#include <soc/itss.h>
#include <soc/pcr_ids.h>
#define IOSF_ITSS_PORT_ID 0xd0
#define ITSS_MAX_IRQ 119
#define IPC0 0x3200
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#define PCR_IPC0_CONF 0x3200
void itss_set_irq_polarity(int irq, int active_low)
{
uint32_t mask;
uint32_t val;
uint16_t reg;
const uint16_t port = IOSF_ITSS_PORT_ID;
const uint16_t port = PID_ITSS;
if (irq < 0 || irq > ITSS_MAX_IRQ)
return;
reg = IPC0 + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
reg = PCR_IPC0_CONF + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
mask = 1 << (irq % IRQS_PER_IPC);
val = iosf_read(port, reg);
val &= ~mask;
/* Setting the bit makes the IRQ active low. */
val |= active_low ? mask : 0;
iosf_write(port, reg, val);
pcr_rmw32(port, reg, ~mask, (active_low ? mask : 0));
}
static uint32_t irq_snapshot[NUM_IPC_REGS];
@ -52,7 +47,7 @@ void itss_snapshot_irq_polarities(int start, int end)
int i;
int reg_start;
int reg_end;
const uint16_t port = IOSF_ITSS_PORT_ID;
const uint16_t port = PID_ITSS;
if (start < 0 || start > ITSS_MAX_IRQ ||
end < 0 || end > ITSS_MAX_IRQ || end < start)
@ -62,20 +57,20 @@ void itss_snapshot_irq_polarities(int start, int end)
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
for (i = reg_start; i < reg_end; i++) {
uint16_t reg = IPC0 + sizeof(uint32_t) * i;
irq_snapshot[i] = iosf_read(port, reg);
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
irq_snapshot[i] = pcr_read32(port, reg);
}
}
static void show_irq_polarities(const char *msg)
{
int i;
const uint16_t port = IOSF_ITSS_PORT_ID;
const uint16_t port = PID_ITSS;
printk(BIOS_INFO, "ITSS IRQ Polarities %s:\n", msg);
for (i = 0; i < NUM_IPC_REGS; i++) {
uint16_t reg = IPC0 + sizeof(uint32_t) * i;
printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, iosf_read(port, reg));
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, pcr_read32(port, reg));
}
}
@ -84,7 +79,7 @@ void itss_restore_irq_polarities(int start, int end)
int i;
int reg_start;
int reg_end;
const uint16_t port = IOSF_ITSS_PORT_ID;
const uint16_t port = PID_ITSS;
if (start < 0 || start > ITSS_MAX_IRQ ||
end < 0 || end > ITSS_MAX_IRQ || end < start)
@ -97,7 +92,6 @@ void itss_restore_irq_polarities(int start, int end)
for (i = reg_start; i < reg_end; i++) {
uint32_t mask;
uint32_t val;
uint16_t reg;
int irq_start;
int irq_end;
@ -118,11 +112,8 @@ void itss_restore_irq_polarities(int start, int end)
mask = (((1U << irq_end) - 1) | (1U << irq_end));
mask &= ~((1U << irq_start) - 1);
reg = IPC0 + sizeof(uint32_t) * i;
val = iosf_read(port, reg);
val &= ~mask;
val |= mask & irq_snapshot[i];
iosf_write(port, reg, val);
reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
pcr_rmw32(port, reg, ~mask, (mask & irq_snapshot[i]));
}
show_irq_polarities("After");