soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
Martin Roth
parent
e7ceae7950
commit
ccd8700cac
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@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
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# CPU specific options
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select IOAPIC
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select PCR_COMMON_IOSF_1_0
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select SMP
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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@ -52,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_SMI
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@ -91,9 +93,11 @@ config SOC_INTEL_COMMON_RESET
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bool
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default y
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config IOSF_BASE_ADDRESS
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hex "MMIO Base Address of sideband bus"
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config PCR_BASE_ADDRESS
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hex
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default 0xd0000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config DCACHE_RAM_BASE
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hex "Base address of cache-as-RAM"
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs.h>
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#include <soc/pcr_ids.h>
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#include "gpiolib.asl"
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scope (\_SB) {
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@ -39,8 +40,8 @@ scope (\_SB) {
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_N, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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ShiftLeft (PID_GPIO_N, PCR_PORTID_SHIFT, Local0)
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Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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@ -70,8 +71,8 @@ scope (\_SB) {
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_NW, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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ShiftLeft (PID_GPIO_NW, PCR_PORTID_SHIFT, Local0)
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Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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@ -101,8 +102,8 @@ scope (\_SB) {
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_W, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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ShiftLeft (PID_GPIO_W, PCR_PORTID_SHIFT, Local0)
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Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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@ -132,8 +133,8 @@ scope (\_SB) {
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
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ShiftLeft (GPIO_SW, 16, Local0)
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Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
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ShiftLeft (PID_GPIO_SW, PCR_PORTID_SHIFT, Local0)
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Or (CONFIG_PCR_BASE_ADDRESS, Local0, RBAS)
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Return (^RBUF)
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}
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@ -17,8 +17,8 @@ Scope (\_SB.PCI0) {
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/* 0xD6- is the port address */
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/* 0x600- is the dynamic clock gating control register offset (GENR) */
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OperationRegion (SBMM, SystemMemory,
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Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
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ShiftLeft(0xD6, 16)), 0x0600), 0x18)
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Or ( Or (CONFIG_PCR_BASE_ADDRESS,
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ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
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Field (SBMM, DWordAcc, NoLock, Preserve)
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{
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GENR, 32,
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <intelblocks/pcr.h>
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#include <soc/gpe.h>
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/* Power button. */
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@ -18,21 +18,25 @@
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#include <bootblock_common.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/systemagent.h>
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#include <lib.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/flash_ctrlr.h>
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#include <soc/gpio.h>
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#include <soc/iosf.h>
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#include <soc/mmap_boot.h>
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#include <soc/systemagent.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/uart.h>
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#include <spi-generic.h>
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#include <timestamp.h>
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#define PCR_RTC_CONF 0x3400
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#define PCR_RTC_CONF_UCMOS_EN 0x4
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static const struct pad_config tpm_spi_configs[] = {
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PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
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};
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@ -45,9 +49,7 @@ static void tpm_enable(void)
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static void enable_cmos_upper_bank(void)
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{
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uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG);
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reg |= RTC_CONFIG_UCMOS_ENABLE;
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iosf_write(IOSF_RTC_PORT_ID, RTC_CONFIG, reg);
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pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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@ -57,8 +59,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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bootblock_systemagent_early_init();
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dev = PCH_DEV_P2SB;
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/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
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/* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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@ -17,9 +17,10 @@
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#include <assert.h>
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#include <gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/gpio.h>
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#include <soc/iosf.h>
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#include <soc/itss.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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/* This list must be in order, from highest pad numbers, to lowest pad numbers*/
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@ -31,25 +32,25 @@ static const struct pad_community {
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const char *grp_name;
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} gpio_communities[] = {
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{
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.port = GPIO_SW,
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.port = PID_GPIO_SW,
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.first_pad = SW_OFFSET,
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.num_gpi_regs = NUM_SW_GPI_REGS,
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.gpi_offset = 0,
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.grp_name = "GPIO_GPE_SW",
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}, {
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.port = GPIO_W,
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.port = PID_GPIO_W,
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.first_pad = W_OFFSET,
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.num_gpi_regs = NUM_W_GPI_REGS,
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.gpi_offset = NUM_SW_GPI_REGS,
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.grp_name = "GPIO_GPE_W",
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}, {
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.port = GPIO_NW,
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.port = PID_GPIO_NW,
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.first_pad = NW_OFFSET,
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.num_gpi_regs = NUM_NW_GPI_REGS,
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.gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
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.grp_name = "GPIO_GPE_NW",
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}, {
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.port = GPIO_N,
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.port = PID_GPIO_N,
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.first_pad = N_OFFSET,
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.num_gpi_regs = NUM_N_GPI_REGS,
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.gpi_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
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@ -92,7 +93,7 @@ static void gpio_configure_itss(const struct pad_config *cfg,
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if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC))
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return;
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irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t));
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irq = pcr_read32(port, pad_cfg_offset + sizeof(uint32_t));
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irq &= PAD_CFG1_IRQ_MASK;
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if (!irq) {
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printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n",
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@ -106,7 +107,6 @@ static void gpio_configure_itss(const struct pad_config *cfg,
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static void gpio_configure_owner(const struct pad_config *cfg,
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uint16_t port, int pin)
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{
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uint32_t val;
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uint16_t hostsw_reg;
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/* The 4th bit in pad_config 1 (RO) is used to indicate if the pad
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@ -119,9 +119,7 @@ static void gpio_configure_owner(const struct pad_config *cfg,
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* HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership.
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*/
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hostsw_reg = HOSTSW_OWN_REG_BASE + ((pin / 32) * sizeof(uint32_t));
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val = iosf_read(port, hostsw_reg);
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val |= 1 << (pin % 32);
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iosf_write(port, hostsw_reg, val);
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pcr_or32(port, hostsw_reg, (1 << (pin % 32)));
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}
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static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
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@ -137,15 +135,13 @@ static void gpi_enable_smi(const struct pad_config *cfg, uint16_t port, int pin)
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group = pin / GPIO_MAX_NUM_PER_GROUP;
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sts_reg = GPI_SMI_STS_OFFSET(group);
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value = iosf_read(port, sts_reg);
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value = pcr_read32(port, sts_reg);
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/* Write back 1 to reset the sts bits */
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iosf_write(port, sts_reg, value);
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pcr_write32(port, sts_reg, value);
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/* Set enable bits */
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en_reg = GPI_SMI_EN_OFFSET(group);
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value = iosf_read(port, en_reg);
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value |= 1 << (pin % GPIO_MAX_NUM_PER_GROUP);
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iosf_write(port, en_reg, value);
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pcr_or32(port, en_reg, (1 << (pin % GPIO_MAX_NUM_PER_GROUP)));
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}
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void gpio_configure_pad(const struct pad_config *cfg)
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@ -162,8 +158,8 @@ void gpio_configure_pad(const struct pad_config *cfg)
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dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK)
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<< PAD_CFG1_IOSSTATE_SHIFT;
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iosf_write(comm->port, config_offset, cfg->config0);
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iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);
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pcr_write32(comm->port, config_offset, cfg->config0);
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pcr_write32(comm->port, config_offset + sizeof(uint32_t), dw1);
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gpio_configure_itss(cfg, comm->port, config_offset);
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gpio_configure_owner(cfg, comm->port, cfg->pad - comm->first_pad);
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@ -186,7 +182,8 @@ void *gpio_dwx_address(const uint16_t pad)
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* returns - address of GPIO
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*/
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const struct pad_community *comm = gpio_get_community(pad);
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return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad));
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return pcr_reg_address(comm->port,
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PAD_CFG_OFFSET(pad - comm->first_pad));
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}
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void gpio_input_pulldown(gpio_t gpio)
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@ -219,21 +216,18 @@ int gpio_get(gpio_t gpio_num)
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const struct pad_community *comm = gpio_get_community(gpio_num);
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uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
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reg = iosf_read(comm->port, config_offset);
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reg = pcr_read32(comm->port, config_offset);
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return !!(reg & PAD_CFG0_RX_STATE);
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}
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void gpio_set(gpio_t gpio_num, int value)
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{
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uint32_t reg;
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const struct pad_community *comm = gpio_get_community(gpio_num);
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uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad);
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reg = iosf_read(comm->port, config_offset);
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reg &= ~PAD_CFG0_TX_STATE;
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reg |= !!value & PAD_CFG0_TX_STATE;
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iosf_write(comm->port, config_offset, reg);
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pcr_rmw32(comm->port, config_offset,
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~PAD_CFG0_TX_STATE, (!!value & PAD_CFG0_TX_STATE));
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}
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const char *gpio_acpi_path(gpio_t gpio_num)
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@ -241,13 +235,13 @@ const char *gpio_acpi_path(gpio_t gpio_num)
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const struct pad_community *comm = gpio_get_community(gpio_num);
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switch (comm->port) {
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case GPIO_N:
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case PID_GPIO_N:
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return "\\_SB.GPO0";
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case GPIO_NW:
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case PID_GPIO_NW:
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return "\\_SB.GPO1";
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case GPIO_W:
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case PID_GPIO_W:
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return "\\_SB.GPO2";
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case GPIO_SW:
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case PID_GPIO_SW:
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return "\\_SB.GPO3";
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}
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@ -259,13 +253,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num)
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const struct pad_community *comm = gpio_get_community(gpio_num);
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switch (comm->port) {
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case GPIO_N:
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case PID_GPIO_N:
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return PAD_N(gpio_num);
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case GPIO_NW:
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case PID_GPIO_NW:
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return PAD_NW(gpio_num);
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case GPIO_W:
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case PID_GPIO_W:
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return PAD_W(gpio_num);
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case GPIO_SW:
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case PID_GPIO_SW:
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return PAD_SW(gpio_num);
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}
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@ -315,13 +309,13 @@ void gpi_clear_get_smi_status(struct gpi_status *sts)
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num_groups = comm->num_gpi_regs;
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index = comm->gpi_offset;
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for (group = 0; group < num_groups; group++, index++) {
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sts_value = iosf_read(gpio_communities[i].port,
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sts_value = pcr_read32(gpio_communities[i].port,
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GPI_SMI_STS_OFFSET(group));
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en_value = iosf_read(gpio_communities[i].port,
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en_value = pcr_read32(gpio_communities[i].port,
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GPI_SMI_EN_OFFSET(group));
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sts->grp[index] = sts_value & en_value;
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/* Clear the set status bits. */
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iosf_write(gpio_communities[i].port,
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pcr_write32(gpio_communities[i].port,
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GPI_SMI_STS_OFFSET(group), sts->grp[index]);
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}
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}
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@ -376,7 +370,6 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
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int i;
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uint32_t misccfg_mask;
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uint32_t misccfg_value;
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uint32_t value;
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int ret;
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/* Get the group here for community specific MISCCFG register.
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@ -412,9 +405,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
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for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) {
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const struct pad_community *comm = &gpio_communities[i];
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value = iosf_read(comm->port, GPIO_MISCCFG);
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value &= misccfg_mask;
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value |= misccfg_value;
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iosf_write(comm->port, GPIO_MISCCFG, value);
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pcr_rmw32(comm->port, GPIO_MISCCFG,
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misccfg_mask, misccfg_value);
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}
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}
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@ -129,13 +129,6 @@
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#define PAD_CFG_BASE 0x500
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#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
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/* IOSF port numbers for GPIO comminuties*/
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#define GPIO_SW 0xc0
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#define GPIO_S 0xc2
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#define GPIO_NW 0xc4
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#define GPIO_N 0xc5
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#define GPIO_W 0xc7
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#define GPI_SMI_STS_0 0x140
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#define GPI_SMI_EN_0 0x150
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#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4))
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@ -20,7 +20,7 @@
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#include <commonlib/helpers.h>
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#define P2SB_BAR CONFIG_IOSF_BASE_ADDRESS
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#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
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#define P2SB_SIZE (16 * MiB)
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#define MCH_BASE_ADDR 0xfed10000
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#define MCH_BASE_SIZE (32 * KiB)
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@ -1,42 +0,0 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_APOLLOLAKE_IOSF_H_
|
||||
#define _SOC_APOLLOLAKE_IOSF_H_
|
||||
|
||||
#include <arch/io.h>
|
||||
|
||||
#define IOSF_RTC_PORT_ID 0xD1
|
||||
#define RTC_CONFIG 0x3400
|
||||
#define RTC_CONFIG_UCMOS_ENABLE (1 << 2)
|
||||
|
||||
static inline void *iosf_address(uint16_t port, uint16_t reg)
|
||||
{
|
||||
uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
|
||||
return (void *)addr;
|
||||
}
|
||||
|
||||
static inline void iosf_write(uint16_t port, uint16_t reg, uint32_t val)
|
||||
{
|
||||
write32(iosf_address(port, reg), val);
|
||||
}
|
||||
|
||||
static inline uint32_t iosf_read(uint16_t port, uint16_t reg)
|
||||
{
|
||||
return read32(iosf_address(port, reg));
|
||||
}
|
||||
#endif /* _SOC_APOLLOLAKE_IOSF_H_ */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOC_INTEL_APL_PCR_H
|
||||
#define SOC_INTEL_APL_PCR_H
|
||||
|
||||
/*
|
||||
* Port ids.
|
||||
*/
|
||||
#define PID_GPIO_SW 0xC0
|
||||
#define PID_GPIO_S 0xC2
|
||||
#define PID_GPIO_NW 0xC4
|
||||
#define PID_GPIO_N 0xC5
|
||||
#define PID_GPIO_W 0xC7
|
||||
#define PID_ITSS 0xD0
|
||||
#define PID_RTC 0xD1
|
||||
|
||||
#endif /* SOC_INTEL_APL_PCR_H */
|
||||
|
|
@ -15,34 +15,29 @@
|
|||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <console/console.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <stdint.h>
|
||||
#include <soc/iosf.h>
|
||||
#include <soc/itss.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
#define IOSF_ITSS_PORT_ID 0xd0
|
||||
#define ITSS_MAX_IRQ 119
|
||||
#define IPC0 0x3200
|
||||
#define IRQS_PER_IPC 32
|
||||
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
|
||||
#define ITSS_MAX_IRQ 119
|
||||
#define IRQS_PER_IPC 32
|
||||
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
|
||||
#define PCR_IPC0_CONF 0x3200
|
||||
|
||||
void itss_set_irq_polarity(int irq, int active_low)
|
||||
{
|
||||
uint32_t mask;
|
||||
uint32_t val;
|
||||
uint16_t reg;
|
||||
const uint16_t port = IOSF_ITSS_PORT_ID;
|
||||
const uint16_t port = PID_ITSS;
|
||||
|
||||
if (irq < 0 || irq > ITSS_MAX_IRQ)
|
||||
return;
|
||||
|
||||
reg = IPC0 + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
|
||||
reg = PCR_IPC0_CONF + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
|
||||
mask = 1 << (irq % IRQS_PER_IPC);
|
||||
|
||||
val = iosf_read(port, reg);
|
||||
val &= ~mask;
|
||||
/* Setting the bit makes the IRQ active low. */
|
||||
val |= active_low ? mask : 0;
|
||||
iosf_write(port, reg, val);
|
||||
pcr_rmw32(port, reg, ~mask, (active_low ? mask : 0));
|
||||
}
|
||||
|
||||
static uint32_t irq_snapshot[NUM_IPC_REGS];
|
||||
|
|
@ -52,7 +47,7 @@ void itss_snapshot_irq_polarities(int start, int end)
|
|||
int i;
|
||||
int reg_start;
|
||||
int reg_end;
|
||||
const uint16_t port = IOSF_ITSS_PORT_ID;
|
||||
const uint16_t port = PID_ITSS;
|
||||
|
||||
if (start < 0 || start > ITSS_MAX_IRQ ||
|
||||
end < 0 || end > ITSS_MAX_IRQ || end < start)
|
||||
|
|
@ -62,20 +57,20 @@ void itss_snapshot_irq_polarities(int start, int end)
|
|||
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
|
||||
|
||||
for (i = reg_start; i < reg_end; i++) {
|
||||
uint16_t reg = IPC0 + sizeof(uint32_t) * i;
|
||||
irq_snapshot[i] = iosf_read(port, reg);
|
||||
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
|
||||
irq_snapshot[i] = pcr_read32(port, reg);
|
||||
}
|
||||
}
|
||||
|
||||
static void show_irq_polarities(const char *msg)
|
||||
{
|
||||
int i;
|
||||
const uint16_t port = IOSF_ITSS_PORT_ID;
|
||||
const uint16_t port = PID_ITSS;
|
||||
|
||||
printk(BIOS_INFO, "ITSS IRQ Polarities %s:\n", msg);
|
||||
for (i = 0; i < NUM_IPC_REGS; i++) {
|
||||
uint16_t reg = IPC0 + sizeof(uint32_t) * i;
|
||||
printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, iosf_read(port, reg));
|
||||
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
|
||||
printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, pcr_read32(port, reg));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -84,7 +79,7 @@ void itss_restore_irq_polarities(int start, int end)
|
|||
int i;
|
||||
int reg_start;
|
||||
int reg_end;
|
||||
const uint16_t port = IOSF_ITSS_PORT_ID;
|
||||
const uint16_t port = PID_ITSS;
|
||||
|
||||
if (start < 0 || start > ITSS_MAX_IRQ ||
|
||||
end < 0 || end > ITSS_MAX_IRQ || end < start)
|
||||
|
|
@ -97,7 +92,6 @@ void itss_restore_irq_polarities(int start, int end)
|
|||
|
||||
for (i = reg_start; i < reg_end; i++) {
|
||||
uint32_t mask;
|
||||
uint32_t val;
|
||||
uint16_t reg;
|
||||
int irq_start;
|
||||
int irq_end;
|
||||
|
|
@ -118,11 +112,8 @@ void itss_restore_irq_polarities(int start, int end)
|
|||
mask = (((1U << irq_end) - 1) | (1U << irq_end));
|
||||
mask &= ~((1U << irq_start) - 1);
|
||||
|
||||
reg = IPC0 + sizeof(uint32_t) * i;
|
||||
val = iosf_read(port, reg);
|
||||
val &= ~mask;
|
||||
val |= mask & irq_snapshot[i];
|
||||
iosf_write(port, reg, val);
|
||||
reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
|
||||
pcr_rmw32(port, reg, ~mask, (mask & irq_snapshot[i]));
|
||||
}
|
||||
|
||||
show_irq_polarities("After");
|
||||
|
|
|
|||
Loading…
Reference in New Issue