move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
this patch also slightly changes it so we have a single cache_as_ram.inc which requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
1abf46c74e
commit
ccdd20a539
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@ -127,7 +127,7 @@ crt0s += $(cpu_incs)
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# FIXME move to CPU_INTEL_SOCKET_MPGA604
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#
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ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
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crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
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crt0s += $(src)/cpu/intel/car/cache_as_ram.inc
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endif
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ifeq ($(CONFIG_LLSHELL),y)
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@ -126,6 +126,19 @@ clear_fixed_var_mtrr:
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wrmsr
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jmp clear_fixed_var_mtrr
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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@ -289,48 +302,118 @@ lout:
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call stage1_main
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/* We will not go back */
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call main
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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.align 0x1000
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.code16
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.global LogicalAP_SIPI
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LogicalAP_SIPI:
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// cr0 register is shared among the logical processors;
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// so clear CD & NW bits so that the BSP's cr0 register
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// controls the cache behavior
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// Note: The cache behavior is determined by "OR" result
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// of the cr0 registers of the logical processors
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/*
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FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
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It is only needed if we want to go back
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*/
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/* We don't need cache as ram for now on */
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/* disable cache */
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movl %cr0, %eax
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andl $0x9FFFFFFF, %eax
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orl $(0x1<<30),%eax
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movl %eax, %cr0
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finit
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// Set the semaphore to indicate the Logical AP is done
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// with CAR specific initialization
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movl $0x250, %ecx
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movl $0x06, %eax
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/* clear sth */
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movl $0x269, %ecx /* fix4k_c8000*/
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xorl %edx, %edx
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xorl %eax, %eax
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wrmsr
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// Halt this AP
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cli
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Halt_LogicalAP:
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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movl $0x268, %ecx /* fix4k_c0000*/
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wrmsr
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#endif
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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movl $0x2ff, %ecx
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// movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Disable Fixed MTRRs */
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movl $0x00000800, %eax
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wrmsr
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#if defined(CLEAR_FIRST_1M_RAM)
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/* enable caching for first 1M using variable mtrr */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(0 | 1), %eax
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// movl $(0 | MTRR_TYPE_WRCOMB), %eax
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wrmsr
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movl $0x201, %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax
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wrmsr
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#endif
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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#if defined(CLEAR_FIRST_1M_RAM)
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/* clear the first 1M */
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movl $0x0, %edi
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cld
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movl $(0x100000>>2), %ecx
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xorl %eax, %eax
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rep stosl
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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movl %eax, %cr0
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/* enable caching for first 1M using variable mtrr */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(0 | 6), %eax
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// movl $(0 | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x201, %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax
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wrmsr
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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invd
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/* FIXME: I hope we don't need to change esp and ebp value here, so we
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* can restore value from mmx sse back But the problem is the range is
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* some io related, So don't go back
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*/
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#endif
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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cld /* clear direction flag */
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movl %ebp, %esi
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/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
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* makes sure that we stay completely within the 1M-64K of memory that we
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* preserve for suspend/resume.
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*/
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#ifndef HIGH_MEMORY_SAVE
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#warning Need a central place for HIGH_MEMORY_SAVE
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#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
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#endif
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movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
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movl %esp, %ebp
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pushl %esi
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call copy_and_run
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.Lhlt:
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post_code(0xee)
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hlt
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jmp Halt_LogicalAP
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.code32
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.CacheAsRam_out:
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jmp .Lhlt
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@ -1,89 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/stages.h>
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/* called from assembler code */
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void stage1_main(unsigned long bist);
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/* from romstage.c */
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void real_main(unsigned long bist);
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void stage1_main(unsigned long bist)
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{
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unsigned int cpu_reset = 0;
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real_main(bist);
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/* No servicable parts below this line .. */
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#ifdef CAR_DEBUG
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n"
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: "=a" (v_esp)
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);
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printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
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#endif
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printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
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printk(BIOS_SPEW, "No cache as ram now - ");
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/* store cpu_reset to ebx */
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__asm__ volatile (
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"movl %0, %%ebx\n\t"
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::"a" (cpu_reset)
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);
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#undef CLEAR_FIRST_1M_RAM
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#include "cpu/x86/car/cache_as_ram_post.c"
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/* For now: use rambase + 1MB - 64K (counting downwards) as stack. This
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* makes sure that we stay completely within the 1M of memory we
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* preserve with the memcpy above.
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*/
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#ifndef HIGH_MEMORY_SAVE
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#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
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#endif
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__asm__ volatile (
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"movl %0, %%ebp\n"
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"movl %0, %%esp\n"
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:: "a" (CONFIG_RAMBASE + HIGH_MEMORY_SAVE)
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);
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{
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unsigned new_cpu_reset;
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/* get back cpu_reset from ebx */
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__asm__ volatile (
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"movl %%ebx, %0\n"
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:"=a" (new_cpu_reset)
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);
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/* Copy and execute coreboot_ram */
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copy_and_run(new_cpu_reset);
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}
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/* We will not return */
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printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
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}
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@ -7,4 +7,4 @@ subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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cpu_incs += $(src)/cpu/x86/car/cache_as_ram.inc
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cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
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@ -1,86 +0,0 @@
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__asm__ volatile (
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/*
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FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
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It is only needed if we want to go back
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*/
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* clear sth */
|
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"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
|
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"xorl %edx, %edx\n\t"
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"xorl %eax, %eax\n\t"
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"wrmsr\n\t"
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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#endif
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|
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %ecx\n\t"
|
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// "movl $MTRRdefType_MSR, %ecx\n\t"
|
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"xorl %edx, %edx\n\t"
|
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/* Enable Variable and Disable Fixed MTRRs */
|
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"movl $0x00000800, %eax\n\t"
|
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"wrmsr\n\t"
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|
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#if defined(CLEAR_FIRST_1M_RAM)
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/* enable caching for first 1M using variable mtrr */
|
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"movl $0x200, %ecx\n\t"
|
||||
"xorl %edx, %edx\n\t"
|
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"movl $(0 | 1), %eax\n\t"
|
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// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
|
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"wrmsr\n\t"
|
||||
|
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"movl $0x201, %ecx\n\t"
|
||||
"movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
|
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
|
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"wrmsr\n\t"
|
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#endif
|
||||
|
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/* enable cache */
|
||||
"movl %cr0, %eax\n\t"
|
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"andl $0x9fffffff,%eax\n\t"
|
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"movl %eax, %cr0\n\t"
|
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#if defined(CLEAR_FIRST_1M_RAM)
|
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/* clear the first 1M */
|
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"movl $0x0, %edi\n\t"
|
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"cld\n\t"
|
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"movl $(0x100000>>2), %ecx\n\t"
|
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"xorl %eax, %eax\n\t"
|
||||
"rep stosl\n\t"
|
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|
||||
/* disable cache */
|
||||
"movl %cr0, %eax\n\t"
|
||||
"orl $(0x1<<30),%eax\n\t"
|
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"movl %eax, %cr0\n\t"
|
||||
|
||||
/* enable caching for first 1M using variable mtrr */
|
||||
"movl $0x200, %ecx\n\t"
|
||||
"xorl %edx, %edx\n\t"
|
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"movl $(0 | 6), %eax\n\t"
|
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// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
|
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"wrmsr\n\t"
|
||||
|
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"movl $0x201, %ecx\n\t"
|
||||
"movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
|
||||
"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
|
||||
/* enable cache */
|
||||
"movl %cr0, %eax\n\t"
|
||||
"andl $0x9fffffff,%eax\n\t"
|
||||
"movl %eax, %cr0\n\t"
|
||||
"invd\n\t"
|
||||
|
||||
/*
|
||||
FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
|
||||
But the problem is the range is some io related, So don't go back
|
||||
*/
|
||||
#endif
|
||||
);
|
||||
|
|
@ -97,9 +97,7 @@ static void mb_early_setup(void)
|
|||
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
|
||||
}
|
||||
|
||||
#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
|
||||
|
||||
void real_main(unsigned long bist)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
if (bist == 0) {
|
||||
if (memory_initialized()) {
|
||||
|
|
|
|||
|
|
@ -96,9 +96,7 @@ static void mb_early_setup(void)
|
|||
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
|
||||
}
|
||||
|
||||
#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
|
||||
|
||||
void real_main(unsigned long bist)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
if (bist == 0) {
|
||||
if (memory_initialized()) {
|
||||
|
|
|
|||
|
|
@ -63,9 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "northbridge/intel/e7501/reset_test.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
|
||||
|
||||
void stage1_main(unsigned long bist)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{
|
||||
|
|
@ -97,8 +95,7 @@ void stage1_main(unsigned long bist)
|
|||
// setup_s2735_resource_map();
|
||||
|
||||
if(bios_reset_detected()) {
|
||||
cpu_reset = 1;
|
||||
goto cpu_reset_x;
|
||||
hard_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
|
@ -119,94 +116,5 @@ void stage1_main(unsigned long bist)
|
|||
#if 1
|
||||
dump_pci_device(PCI_DEV(0, 0, 0));
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
{
|
||||
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
|
||||
unsigned v_esp;
|
||||
__asm__ volatile (
|
||||
"movl %%esp, %0\n\t"
|
||||
: "=a" (v_esp)
|
||||
);
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
|
||||
#else
|
||||
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
cpu_reset_x:
|
||||
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset);
|
||||
#else
|
||||
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n");
|
||||
#endif
|
||||
|
||||
if(cpu_reset == 0) {
|
||||
print_debug("Clearing initial memory region: ");
|
||||
}
|
||||
print_debug("No cache as ram now - ");
|
||||
|
||||
/* store cpu_reset to ebx */
|
||||
__asm__ volatile (
|
||||
"movl %0, %%ebx\n\t"
|
||||
::"a" (cpu_reset)
|
||||
);
|
||||
|
||||
if(cpu_reset==0) {
|
||||
#define CLEAR_FIRST_1M_RAM 1
|
||||
#include "cpu/x86/car/cache_as_ram_post.c"
|
||||
}
|
||||
else {
|
||||
#undef CLEAR_FIRST_1M_RAM
|
||||
#include "cpu/x86/car/cache_as_ram_post.c"
|
||||
}
|
||||
|
||||
__asm__ volatile (
|
||||
/* set new esp */ /* before CONFIG_RAMBASE */
|
||||
"subl %0, %%ebp\n\t"
|
||||
"subl %0, %%esp\n\t"
|
||||
::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
|
||||
);
|
||||
|
||||
{
|
||||
unsigned new_cpu_reset;
|
||||
|
||||
/* get back cpu_reset from ebx */
|
||||
__asm__ volatile (
|
||||
"movl %%ebx, %0\n\t"
|
||||
:"=a" (new_cpu_reset)
|
||||
);
|
||||
|
||||
/* We can not go back any more, we lost old stack data in cache as ram*/
|
||||
if(new_cpu_reset==0) {
|
||||
print_debug("Use Ram as Stack now - done\n");
|
||||
} else
|
||||
{
|
||||
print_debug("Use Ram as Stack now - \n");
|
||||
}
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
|
||||
#else
|
||||
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n");
|
||||
#endif
|
||||
|
||||
#ifdef DEACTIVATE_CAR
|
||||
print_debug("Deactivating CAR");
|
||||
#include DEACTIVATE_CAR_FILE
|
||||
print_debug(" - Done.\n");
|
||||
#endif
|
||||
/*copy and execute coreboot_ram */
|
||||
copy_and_run(new_cpu_reset);
|
||||
/* We will not return */
|
||||
}
|
||||
#endif
|
||||
|
||||
print_debug("should not be here -\n");
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ void EmbedComInit()
|
|||
|
||||
/* cache_as_ram.inc jump to here
|
||||
*/
|
||||
void stage1_main(unsigned long bist)
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
unsigned cpu_reset = 0;
|
||||
u16 boot_mode;
|
||||
|
|
@ -555,104 +555,5 @@ g) Rx73h = 32h
|
|||
"wrmsr\n\t"
|
||||
);*/
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
the following code is copied from src/mainboard/tyan/s2735/romstage.c
|
||||
Only the code around CLEAR_FIRST_1M_RAM is changed.
|
||||
I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c"
|
||||
the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere,
|
||||
and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area.
|
||||
|
||||
So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version
|
||||
*/
|
||||
#if 1
|
||||
{
|
||||
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
|
||||
unsigned v_esp;
|
||||
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
|
||||
);
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
|
||||
#else
|
||||
print_debug("v_esp=");
|
||||
print_debug_hex32(v_esp);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
cpu_reset_x:
|
||||
// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy
|
||||
//stack
|
||||
cpu_reset = 0;
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
|
||||
#else
|
||||
print_debug("cpu_reset = ");
|
||||
print_debug_hex32(cpu_reset);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
|
||||
if (cpu_reset == 0) {
|
||||
print_debug("Clearing initial memory region: ");
|
||||
}
|
||||
print_debug("No cache as ram now - ");
|
||||
|
||||
/* store cpu_reset to ebx */
|
||||
__asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset)
|
||||
);
|
||||
|
||||
|
||||
/* cancel these lines, CLEAR_FIRST_1M_RAM cause the cpu/x86/car/cache_as_ram_post.c stop at somewhere
|
||||
|
||||
if(cpu_reset==0) {
|
||||
#define CLEAR_FIRST_1M_RAM 1
|
||||
#include "cpu/via/car/cache_as_ram_post.c"
|
||||
}
|
||||
else {
|
||||
#undef CLEAR_FIRST_1M_RAM
|
||||
#include "cpu/via/car/cache_as_ram_post.c"
|
||||
}
|
||||
*/
|
||||
#include "cpu/via/car/cache_as_ram_post.c"
|
||||
//#include "cpu/x86/car/cache_as_ram_post.c"
|
||||
__asm__ volatile (
|
||||
/* set new esp *//* before CONFIG_RAMBASE */
|
||||
"subl %0, %%ebp\n\t"
|
||||
"subl %0, %%esp\n\t"::
|
||||
"a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) -
|
||||
CONFIG_RAMBASE)
|
||||
);
|
||||
|
||||
{
|
||||
unsigned new_cpu_reset;
|
||||
|
||||
/* get back cpu_reset from ebx */
|
||||
__asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset)
|
||||
);
|
||||
|
||||
/* We can not go back any more, we lost old stack data in cache as ram */
|
||||
if (new_cpu_reset == 0) {
|
||||
print_debug("Use Ram as Stack now - done\n");
|
||||
} else {
|
||||
print_debug("Use Ram as Stack now - \n");
|
||||
}
|
||||
#if CONFIG_USE_PRINTK_IN_CAR
|
||||
printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
|
||||
#else
|
||||
print_debug("new_cpu_reset = ");
|
||||
print_debug_hex32(new_cpu_reset);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
/*copy and execute coreboot_ram */
|
||||
copy_and_run(new_cpu_reset);
|
||||
/* We will not return */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
print_debug("should not be here -\n");
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue