s2735 half update
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
a1653cfea5
commit
ccf0bc01aa
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@ -7,4 +7,4 @@ dir /cpu/x86/lapic
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dir /cpu/x86/cache
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dir /cpu/x86/cache
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dir /cpu/intel/microcode
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dir /cpu/intel/microcode
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dir /cpu/intel/hyperthreading
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dir /cpu/intel/hyperthreading
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driver model_f1x_init.o
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driver model_f2x_init.o
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@ -30,7 +30,7 @@ static uint32_t microcode_updates[] = {
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};
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};
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static void model_f2x_init(device_t dev)
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static void model_f2x_init(device_t cpu)
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{
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{
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/* Turn on caching if we haven't already */
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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x86_enable_cache();
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@ -48,7 +48,7 @@ static void model_f2x_init(device_t dev)
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};
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};
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static struct device_operations cpu_dev_ops = {
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static struct device_operations cpu_dev_ops = {
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.init = model_f1x_init,
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.init = model_f2x_init,
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};
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};
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static struct cpu_device_id cpu_table[] = {
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_INTEL, 0x0f22 },
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{ X86_VENDOR_INTEL, 0x0f22 },
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@ -1,4 +1,4 @@
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extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control;
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extern struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops;
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struct cpu_intel_socket_mPGA604_533Mhz_config {
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struct cpu_intel_socket_mPGA604_533Mhz_config {
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};
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};
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@ -2,6 +2,6 @@
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#include "chip.h"
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#include "chip.h"
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struct chip_operations cpu_intel_socket_mPGA604_533Mhz_control = {
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struct chip_operations cpu_intel_socket_mPGA604_533Mhz_ops = {
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.name = "socket mPGA604_533Mhz",
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.name = "socket mPGA604_533Mhz",
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};
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};
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@ -1,230 +1,200 @@
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uses HAVE_MP_TABLE
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##
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uses HAVE_PIRQ_TABLE
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## Compute the location and size of where this firmware image
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uses USE_FALLBACK_IMAGE
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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uses LB_CKS_RANGE_START
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##
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uses LB_CKS_RANGE_END
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if USE_FALLBACK_IMAGE
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uses LB_CKS_LOC
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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uses MAINBOARD
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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uses ARCH
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else
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uses HARD_RESET_BUS
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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uses HARD_RESET_DEVICE
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default ROM_SECTION_OFFSET = 0
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uses HARD_RESET_FUNCTION
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end
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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config chip.h
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register "fixup_scsi" = "1"
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register "fixup_vga" = "1"
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##
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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driver mainboard.o
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driver mainboard.o
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#dir /drvers/adaptec/7902
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#dir /drivers/si/3114
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#dir /drivers/intel/82551_ipmi
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#dir /drivers/ati/ragexl
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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#object reset.o
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#default HARD_RESET_BUS=1
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#default HARD_RESET_DEVICE=4
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#default HARD_RESET_FUNCTION=0
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#
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arch i386 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/i386/bist32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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#mainboardinit cpu/p6/earlymtrr.inc
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit ./failover.inc
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end
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#
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#
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###
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### Setup the serial port
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###
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit cpu/i386/bist32_fail.inc
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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##
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## Romcc output
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##
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makerule ./failover.E
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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end
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makerule ./failover.inc
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makerule ./failover.inc
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depends "./romcc ./failover.E"
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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end
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makerule ./auto.E
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h"
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depends "$(MAINBOARD)/auto.c option_table.h "
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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end
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makerule ./auto.inc
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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depends "./auto.E ./romcc"
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action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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# action "./romcc -O2 ./auto.E > auto.inc"
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end
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end
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mainboardinit cpu/p6/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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##
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mainboardinit cpu/p6/disable_mmx_sse.inc
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## Build our 16 bit and 32 bit linuxBIOS entry code
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#
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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###
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### Include the secondary Configuration files
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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config chip.h
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# sample config for tyan/s2735
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chip northbridge/intel/e7501
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chip northbridge/intel/e7501
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device pci_domain 0
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device pci_domain 0 on
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device pci 0.0 on end
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.1 on end
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device pci 2.0 on
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device pci 2.0 on
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chip southbridge/intel/i82870
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chip southbridge/intel/i82870
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device pci 1c.0
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device pci 1c.0 on end
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device pci 1d.0
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device pci 1d.0 on end
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device pci 1e.0
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device pci 1e.0 on end
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device pci 1f.0
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device pci 1f.0 on end
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end
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end
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end
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end
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device pci 6.0 on end
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device pci 6.0 on end
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chip southbridge/intel/i82801er
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chip southbridge/intel/i82801er
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device pci 1d.0 on end
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.2 on end
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device pci 1d.3 on end
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device pci 1d.3 on end
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device pci 1d.7 on end
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device pci 1d.7 on end
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device pci 1e.0 on end
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device pci 1e.0 on end
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device pci 1f.0 on
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device pci 1f.0 on
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# device pci 8.0 end
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# device pci 8.0 end
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chip winbond/w83627hf
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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io 0x60 = 0x3f0
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irq 0x70 = 6
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irq 0x70 = 6
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drq 0x74 = 2
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drq 0x74 = 2
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end
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end
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device pnp 2e.1 off # Parallel Port
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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io 0x60 = 0x378
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irq 0x70 = 7
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irq 0x70 = 7
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end
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end
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device pnp 2e.2 on # Com1
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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io 0x60 = 0x3f8
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irq 0x70 = 4
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irq 0x70 = 4
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end
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end
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device pnp 2e.3 off # Com2
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0x70 = 3
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end
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end
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device pnp 2e.5 on # Keyboard
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x60 = 0x60
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io 0x62 = 0x64
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x70 = 1
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irq 0x72 = 12
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irq 0x72 = 12
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end
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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io 0x60 = 0x290
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end
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end
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end
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end
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end
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end
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device pci 1f.1 off end
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device pci 1f.1 off end
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device pci 1f.2 on end
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device pci 1f.2 on end
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device pci 1f.3 on end
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device pci 1f.3 on end
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device pci 1f.5 off end
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device pci 1f.5 off end
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device pci 1f.6 off end
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device pci 1f.6 off end
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end
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end
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end
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end
|
||||||
device apic_cluster 0
|
device apic_cluster 0 on
|
||||||
chip cpu/intel/socket_mPGA604_533Mhz
|
chip cpu/intel/socket_mPGA604_533Mhz
|
||||||
apic 0
|
device apic 0 on end
|
||||||
end
|
end
|
||||||
chip cpu/intel/socket_mPGA604_533Mhz
|
chip cpu/intel/socket_mPGA604_533Mhz
|
||||||
apic 6
|
device apic 6 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
dir /pc80
|
|
||||||
#dir /bioscall
|
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,12 @@
|
||||||
#define ASSEMBLY 1
|
#define ASSEMBLY 1
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <device/pci_def.h>
|
#include <device/pci_def.h>
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <device/pnp_def.h>
|
#include <device/pnp_def.h>
|
||||||
#include <arch/romcc_io.h>
|
#include <arch/romcc_io.h>
|
||||||
#include <arch/smp/lapic.h>
|
#include <cpu/x86/lapic.h>
|
||||||
|
#include <arch/cpu.h>
|
||||||
#include "option_table.h"
|
#include "option_table.h"
|
||||||
#include "pc80/mc146818rtc_early.c"
|
#include "pc80/mc146818rtc_early.c"
|
||||||
#include "pc80/serial.c"
|
#include "pc80/serial.c"
|
||||||
|
|
@ -12,17 +14,13 @@
|
||||||
#include "ram/ramtest.c"
|
#include "ram/ramtest.c"
|
||||||
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
|
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
|
||||||
#include "northbridge/intel/e7501/raminit.h"
|
#include "northbridge/intel/e7501/raminit.h"
|
||||||
|
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||||
#if 1
|
|
||||||
#include "cpu/p6/apic_timer.c"
|
|
||||||
#include "lib/delay.c"
|
#include "lib/delay.c"
|
||||||
#endif
|
#include "cpu/x86/lapic/boot_cpu.c"
|
||||||
|
|
||||||
#include "cpu/p6/boot_cpu.c"
|
|
||||||
#include "northbridge/intel/e7501/debug.c"
|
#include "northbridge/intel/e7501/debug.c"
|
||||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||||
|
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||||
#include "cpu/p6/earlymtrr.c"
|
#include "cpu/x86/bist.h"
|
||||||
|
|
||||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||||
|
|
||||||
|
|
@ -55,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#include "northbridge/intel/e7501/reset_test.c"
|
#include "northbridge/intel/e7501/reset_test.c"
|
||||||
#include "sdram/generic_sdram.c"
|
#include "sdram/generic_sdram.c"
|
||||||
|
|
||||||
static void main(void)
|
static void main(unsigned long bist)
|
||||||
{
|
{
|
||||||
static const struct mem_controller memctrl[] = {
|
static const struct mem_controller memctrl[] = {
|
||||||
{
|
{
|
||||||
|
|
@ -66,14 +64,21 @@ static void main(void)
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
#if 1
|
if (bist == 0) {
|
||||||
enable_lapic();
|
/* Skip this if there was a built in self test failure */
|
||||||
init_timer();
|
early_mtrr_init();
|
||||||
#endif
|
enable_lapic();
|
||||||
|
init_timer();
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||||
uart_init();
|
uart_init();
|
||||||
console_init();
|
console_init();
|
||||||
|
|
||||||
|
/* Halt if there was a built in self test failure */
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
// setup_default_resource_map();
|
// setup_default_resource_map();
|
||||||
#if 0
|
#if 0
|
||||||
print_pci_devices();
|
print_pci_devices();
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
extern struct chip_operations mainboard_tyan_s2735_control;
|
extern struct chip_operations mainboard_tyan_s2735_ops;
|
||||||
|
|
||||||
struct mainboard_tyan_s2735_config {
|
struct mainboard_tyan_s2735_config {
|
||||||
int fixup_scsi;
|
int fixup_scsi;
|
||||||
|
|
|
||||||
|
|
@ -4,22 +4,14 @@
|
||||||
#include <device/pci_ids.h>
|
#include <device/pci_ids.h>
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <arch/romcc_io.h>
|
#include <arch/romcc_io.h>
|
||||||
#include <arch/smp/lapic.h>
|
#include <cpu/x86/lapic.h>
|
||||||
#include "pc80/mc146818rtc_early.c"
|
#include "pc80/mc146818rtc_early.c"
|
||||||
#include "southbridge/intel/i82801er/cmos_failover.c"
|
#include "southbridge/intel/i82801er/cmos_failover.c"
|
||||||
#include "cpu/p6/boot_cpu.c"
|
#include "cpu/x86/lapic/boot_cpu.c"
|
||||||
#include "northbridge/intel/e7501/reset_test.c"
|
#include "northbridge/intel/e7501/reset_test.c"
|
||||||
|
|
||||||
#define HAVE_REGPARM_SUPPORT 0
|
|
||||||
#if HAVE_REGPARM_SUPPORT
|
|
||||||
static unsigned long main(unsigned long bist)
|
static unsigned long main(unsigned long bist)
|
||||||
{
|
{
|
||||||
#else
|
|
||||||
static void main(void)
|
|
||||||
{
|
|
||||||
unsigned long bist = 0;
|
|
||||||
|
|
||||||
#endif
|
|
||||||
/* Is this a deliberate reset by the bios */
|
/* Is this a deliberate reset by the bios */
|
||||||
if (bios_reset_detected() && last_boot_normal()) {
|
if (bios_reset_detected() && last_boot_normal()) {
|
||||||
goto normal_image;
|
goto normal_image;
|
||||||
|
|
@ -51,9 +43,5 @@ static void main(void)
|
||||||
);
|
);
|
||||||
#endif
|
#endif
|
||||||
fallback_image:
|
fallback_image:
|
||||||
#if HAVE_REGPARM_SUPPORT
|
|
||||||
return bist;
|
return bist;
|
||||||
#else
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -139,10 +139,10 @@ static struct device_operations mainboard_operations = {
|
||||||
|
|
||||||
static void enable_dev(device_t dev)
|
static void enable_dev(device_t dev)
|
||||||
{
|
{
|
||||||
dev->ops = &mainboard_ops;
|
dev->ops = &mainboard_operations;
|
||||||
}
|
}
|
||||||
|
|
||||||
struct chip_operations mainboard_tyan_s2735_control = {
|
struct chip_operations mainboard_tyan_s2735_ops = {
|
||||||
.enable_dev = enable_dev,
|
.enable_dev = enable_dev,
|
||||||
.name = "Tyan s2735 mainboard ",
|
.name = "Tyan s2735 mainboard ",
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -4,7 +4,7 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
void *smp_write_config_table(void *v)
|
||||||
{
|
{
|
||||||
static const char sig[4] = "PCMP";
|
static const char sig[4] = "PCMP";
|
||||||
static const char oem[8] = "TYAN ";
|
static const char oem[8] = "TYAN ";
|
||||||
|
|
@ -28,7 +28,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
mc->mpe_checksum = 0;
|
mc->mpe_checksum = 0;
|
||||||
mc->reserved = 0;
|
mc->reserved = 0;
|
||||||
|
|
||||||
smp_write_processors(mc, processor_map);
|
smp_write_processors(mc);
|
||||||
|
|
||||||
|
|
||||||
/*Bus: Bus ID Type*/
|
/*Bus: Bus ID Type*/
|
||||||
|
|
@ -41,19 +41,21 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
/*I/O APICs: APIC ID Version State Address*/
|
/*I/O APICs: APIC ID Version State Address*/
|
||||||
smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
|
smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
|
||||||
{
|
{
|
||||||
struct pci_dev *dev;
|
device_t dev;
|
||||||
uint32_t base;
|
struct resource *res;
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
|
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
if (res) {
|
||||||
smp_write_ioapic(mc, 9, 0x20, base);
|
smp_write_ioapic(mc, 0x09, 0x20, res->base);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
|
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||||
if (dev) {
|
if (dev) {
|
||||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
if (res) {
|
||||||
smp_write_ioapic(mc, 0xa, 0x20, base);
|
smp_write_ioapic(mc, 0x0a, 0x20, res->base);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||||
|
|
@ -157,9 +159,9 @@ Compatibility Bus Address
|
||||||
return smp_next_mpe_entry(mc);
|
return smp_next_mpe_entry(mc);
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
unsigned long write_smp_table(unsigned long addr)
|
||||||
{
|
{
|
||||||
void *v;
|
void *v;
|
||||||
v = smp_write_floating_table(addr);
|
v = smp_write_floating_table(addr);
|
||||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
return (unsigned long)smp_write_config_table(v);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -105,7 +105,7 @@ default LB_CKS_LOC=123
|
||||||
## Only worry about 2 micro processors
|
## Only worry about 2 micro processors
|
||||||
##
|
##
|
||||||
default CONFIG_SMP=1
|
default CONFIG_SMP=1
|
||||||
default CONFIG_MAX_CPUS=2
|
default CONFIG_MAX_CPUS=4
|
||||||
|
|
||||||
##
|
##
|
||||||
## Build code to setup a generic IOAPIC
|
## Build code to setup a generic IOAPIC
|
||||||
|
|
|
||||||
|
|
@ -105,7 +105,7 @@ default LB_CKS_LOC=123
|
||||||
## Only worry about 2 micro processors
|
## Only worry about 2 micro processors
|
||||||
##
|
##
|
||||||
default CONFIG_SMP=1
|
default CONFIG_SMP=1
|
||||||
default CONFIG_MAX_CPUS=2
|
default CONFIG_MAX_CPUS=4
|
||||||
|
|
||||||
##
|
##
|
||||||
## Build code to setup a generic IOAPIC
|
## Build code to setup a generic IOAPIC
|
||||||
|
|
|
||||||
|
|
@ -1,265 +1,43 @@
|
||||||
# Sample config file for
|
# Sample config file for
|
||||||
# the Tyan s2735
|
# the Tyan s2735
|
||||||
# This will make a target directory of ./s2735
|
# This will make a target directory of ./s2735
|
||||||
|
|
||||||
loadoptions
|
|
||||||
|
|
||||||
target s2735
|
target s2735
|
||||||
|
mainboard tyan/s2735
|
||||||
|
|
||||||
uses ARCH
|
# Tyan s2735
|
||||||
uses CONFIG_COMPRESS
|
|
||||||
uses CONFIG_IOAPIC
|
|
||||||
uses CONFIG_ROM_STREAM
|
|
||||||
uses CONFIG_ROM_STREAM_START
|
|
||||||
uses CONFIG_SMP
|
|
||||||
uses CONFIG_UDELAY_TSC
|
|
||||||
uses CPU_FIXUP
|
|
||||||
uses FALLBACK_SIZE
|
|
||||||
uses HAVE_FALLBACK_BOOT
|
|
||||||
uses HAVE_MP_TABLE
|
|
||||||
uses HAVE_PIRQ_TABLE
|
|
||||||
uses i586
|
|
||||||
uses i686
|
|
||||||
uses INTEL_PPRO_MTRR
|
|
||||||
uses HEAP_SIZE
|
|
||||||
uses IRQ_SLOT_COUNT
|
|
||||||
uses MAINBOARD
|
|
||||||
uses MAINBOARD_PART_NUMBER
|
|
||||||
uses MAINBOARD_VENDOR
|
|
||||||
#uses MEMORY_HOLE
|
|
||||||
uses PAYLOAD_SIZE
|
|
||||||
uses _RAMBASE
|
|
||||||
uses _ROMBASE
|
|
||||||
uses ROM_IMAGE_SIZE
|
|
||||||
uses ROM_SECTION_OFFSET
|
|
||||||
uses ROM_SECTION_SIZE
|
|
||||||
uses ROM_SIZE
|
|
||||||
uses STACK_SIZE
|
|
||||||
uses USE_FALLBACK_IMAGE
|
|
||||||
uses USE_OPTION_TABLE
|
|
||||||
uses HAVE_OPTION_TABLE
|
|
||||||
uses CONFIG_CHIP_CONFIGURE
|
|
||||||
|
|
||||||
uses CONFIG_CONSOLE_BTEXT
|
|
||||||
uses CONFIG_CONSOLE_SERIAL8250
|
|
||||||
uses TTYS0_BAUD
|
|
||||||
#SMDC Support
|
|
||||||
#uses CONFIG_CONSOLE_SERIAL8250_2
|
|
||||||
#uses TTYS1_BAUD
|
|
||||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
|
||||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
|
||||||
uses DEBUG
|
|
||||||
uses CONFIG_MAX_CPUS
|
|
||||||
uses CONFIG_LOGICAL_CPUS
|
|
||||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
|
||||||
uses LINUXBIOS_EXTRA_VERSION
|
|
||||||
uses XIP_ROM_SIZE
|
|
||||||
uses XIP_ROM_BASE
|
|
||||||
|
|
||||||
uses CONFIG_FS_STREAM
|
|
||||||
uses CONFIG_IDE
|
|
||||||
|
|
||||||
uses HAVE_HARD_RESET
|
|
||||||
|
|
||||||
#uses CONFIG_VGABIOS
|
|
||||||
#uses CONFIG_REALMODE_IDT
|
|
||||||
#uses CONFIG_PCIBIOS
|
|
||||||
#uses VGABIOS_START
|
|
||||||
#uses SCSIFW_START
|
|
||||||
|
|
||||||
#
|
|
||||||
#uses CONFIG_LSI_SCSI_FW_FIXUP
|
|
||||||
|
|
||||||
option HAVE_OPTION_TABLE=1
|
|
||||||
option HAVE_MP_TABLE=1
|
|
||||||
option CPU_FIXUP=1
|
|
||||||
option CONFIG_UDELAY_TSC=0
|
|
||||||
option i686=1
|
|
||||||
option i586=1
|
|
||||||
option INTEL_PPRO_MTRR=1
|
|
||||||
#option ROM_SIZE=524288
|
|
||||||
option ROM_SIZE=1048576
|
|
||||||
|
|
||||||
option HAVE_HARD_RESET=1
|
|
||||||
|
|
||||||
#option CONFIG_CONSOLE_BTEXT=1
|
|
||||||
#option CONFIG_VGABIOS=1
|
|
||||||
#option CONFIG_REALMODE_IDT=1
|
|
||||||
#option CONFIG_PCIBIOS=1
|
|
||||||
#option VGABIOS_START=0xfff8c000
|
|
||||||
#option SCSIFW_START=0xfff80000
|
|
||||||
|
|
||||||
#option CONFIG_FS_STREAM=1
|
|
||||||
#option CONFIG_IDE=1
|
|
||||||
|
|
||||||
option HAVE_FALLBACK_BOOT=1
|
|
||||||
|
|
||||||
# use the new chip configure code.
|
|
||||||
|
|
||||||
option CONFIG_CHIP_CONFIGURE=1
|
|
||||||
#option CONFIG_LSI_SCSI_FW_FIXUP=1
|
|
||||||
|
|
||||||
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### Build code to export a programmable irq routing table
|
|
||||||
###
|
|
||||||
option HAVE_PIRQ_TABLE=1
|
|
||||||
option IRQ_SLOT_COUNT=15
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### Build code for SMP support
|
|
||||||
### Only worry about 2 micro processors
|
|
||||||
###
|
|
||||||
option CONFIG_SMP=1
|
|
||||||
option CONFIG_MAX_CPUS=4
|
|
||||||
option CONFIG_LOGICAL_CPUS=1
|
|
||||||
option CONFIG_MAX_PHYSICAL_CPUS=2
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### Build code to setup a generic IOAPIC
|
|
||||||
###
|
|
||||||
option CONFIG_IOAPIC=1
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### MEMORY_HOLE instructs earlymtrr.inc to
|
|
||||||
### enable caching from 0-640KB and to disable
|
|
||||||
### caching from 640KB-1MB using fixed MTRRs
|
|
||||||
###
|
|
||||||
### Enabling this option breaks SMP because secondary
|
|
||||||
### CPU identification depends on only variable MTRRs
|
|
||||||
### being enabled.
|
|
||||||
###
|
|
||||||
#option MEMORY_HOLE=0
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### Clean up the motherboard id strings
|
|
||||||
###
|
|
||||||
option MAINBOARD_PART_NUMBER="S2735"
|
|
||||||
option MAINBOARD_VENDOR="Tyan"
|
|
||||||
###
|
|
||||||
### Compute the location and size of where this firmware image
|
|
||||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
|
||||||
###
|
|
||||||
#option FALLBACK_SIZE=524288
|
|
||||||
#option FALLBACK_SIZE=98304
|
|
||||||
option FALLBACK_SIZE=131072
|
|
||||||
|
|
||||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
|
||||||
option ROM_IMAGE_SIZE=65536
|
|
||||||
|
|
||||||
|
|
||||||
###
|
|
||||||
### Compute where this copy of linuxBIOS will start in the boot rom
|
|
||||||
###
|
|
||||||
#
|
|
||||||
###
|
|
||||||
|
|
||||||
## We do use compressed image
|
|
||||||
option CONFIG_COMPRESS=1
|
|
||||||
|
|
||||||
option CONFIG_CONSOLE_SERIAL8250=1
|
|
||||||
option TTYS0_BAUD=115200
|
|
||||||
|
|
||||||
#SMDC support
|
|
||||||
#option CONFIG_CONSOLE_SERIAL8250_2=1
|
|
||||||
#option TTYS1_BAUD=19200
|
|
||||||
|
|
||||||
|
|
||||||
##
|
|
||||||
### Select the linuxBIOS loglevel
|
|
||||||
##
|
|
||||||
## EMERG 1 system is unusable
|
|
||||||
## ALERT 2 action must be taken immediately
|
|
||||||
## CRIT 3 critical conditions
|
|
||||||
## ERR 4 error conditions
|
|
||||||
## WARNING 5 warning conditions
|
|
||||||
## NOTICE 6 normal but significant condition
|
|
||||||
## INFO 7 informational
|
|
||||||
## DEBUG 8 debug-level messages
|
|
||||||
## SPEW 9 Way too many details
|
|
||||||
|
|
||||||
## Request this level of debugging output
|
|
||||||
option DEFAULT_CONSOLE_LOGLEVEL=8
|
|
||||||
## At a maximum only compile in this level of debugging
|
|
||||||
option MAXIMUM_CONSOLE_LOGLEVEL=8
|
|
||||||
|
|
||||||
option DEBUG=1
|
|
||||||
|
|
||||||
#
|
|
||||||
|
|
||||||
## LinuxBIOS C code runs at this location in RAM
|
|
||||||
option _RAMBASE=0x004000
|
|
||||||
|
|
||||||
##
|
|
||||||
## Use a 32K stack
|
|
||||||
##
|
|
||||||
option STACK_SIZE=0x8000
|
|
||||||
|
|
||||||
##
|
|
||||||
## Use a 56K heap
|
|
||||||
##
|
|
||||||
option HEAP_SIZE=0xe000
|
|
||||||
|
|
||||||
#
|
|
||||||
###
|
|
||||||
### Compute the start location and size size of
|
|
||||||
### The linuxBIOS bootloader.
|
|
||||||
###
|
|
||||||
option CONFIG_ROM_STREAM = 1
|
|
||||||
|
|
||||||
#
|
|
||||||
#
|
|
||||||
romimage "normal"
|
romimage "normal"
|
||||||
# 48K for SCSI FW
|
# 48K for SCSI FW
|
||||||
# option ROM_SIZE = 475136
|
# option ROM_SIZE = 475136
|
||||||
# 48K for SCSI FW and 48K for ATI ROM
|
# 48K for SCSI FW and 48K for ATI ROM
|
||||||
# option ROM_SIZE = 425984
|
# option ROM_SIZE = 425984
|
||||||
# 64K for Etherboot
|
# 64K for Etherboot
|
||||||
# option ROM_SIZE = 458752
|
# option ROM_SIZE = 458752
|
||||||
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
|
option USE_FALLBACK_IMAGE=0
|
||||||
option USE_FALLBACK_IMAGE=0
|
option ROM_IMAGE_SIZE=0x10000
|
||||||
option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
|
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
|
||||||
option ROM_SECTION_OFFSET= 0
|
# payload ../../../payloads/tg3--ide_disk.zelf
|
||||||
|
|
||||||
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
|
|
||||||
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
|
||||||
option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
|
|
||||||
|
|
||||||
# option XIP_ROM_SIZE = FALLBACK_SIZE
|
|
||||||
option XIP_ROM_SIZE = 65536
|
|
||||||
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
|
|
||||||
|
|
||||||
mainboard tyan/s2735
|
|
||||||
# payload ../../../payloads/e1000--ide_disk.zelf
|
|
||||||
# payload ../../../payloads/filo.elf
|
# payload ../../../payloads/filo.elf
|
||||||
# payload ../../../payloads/filo_mem.elf
|
# payload ../../../payloads/filo_mem.elf
|
||||||
# payload ../../../payloads/filo_mem_btext.elf
|
# payload ../../../payloads/filo.zelf
|
||||||
# payload ../../../payloads/filo_btext.zelf
|
# payload ../../../payloads/tg3--filo.zelf
|
||||||
payload ../../../payloads/e1000--filo_btext.zelf
|
# payload ../../../payloads/e1000--filo.zelf
|
||||||
|
# payload ../../../payloads/tg3--e1000--filo.zelf
|
||||||
|
payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
|
||||||
end
|
end
|
||||||
|
|
||||||
romimage "fallback"
|
romimage "fallback"
|
||||||
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
|
|
||||||
option USE_FALLBACK_IMAGE=1
|
option USE_FALLBACK_IMAGE=1
|
||||||
option ROM_SECTION_SIZE = FALLBACK_SIZE
|
option ROM_IMAGE_SIZE=0x10000
|
||||||
option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
|
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
|
||||||
|
# payload ../../../payloads/tg3--ide_disk.zelf
|
||||||
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
|
# payload ../../../payloads/filo.elf
|
||||||
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
|
||||||
option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
|
|
||||||
|
|
||||||
# option XIP_ROM_SIZE = FALLBACK_SIZE
|
|
||||||
option XIP_ROM_SIZE = 65536
|
|
||||||
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
|
|
||||||
|
|
||||||
mainboard tyan/s2735
|
|
||||||
# payload ../../../payloads/e1000--ide_disk.zelf
|
|
||||||
# payload ../../../payloads/filo_mem.elf
|
# payload ../../../payloads/filo_mem.elf
|
||||||
# payload ../../../payloads/filo_mem_btext.elf
|
# payload ../../../payloads/filo.zelf
|
||||||
# payload ../../../payloads/e1000_btext.zelf
|
# payload ../../../payloads/tg3--filo.zelf
|
||||||
payload ../../../payloads/e1000--filo_btext.zelf
|
# payload ../../../payloads/e1000--filo.zelf
|
||||||
|
# payload ../../../payloads/tg3--e1000--filo.zelf
|
||||||
|
payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
|
||||||
end
|
end
|
||||||
|
|
||||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
#!/bin/bash
|
#!/bin/bash
|
||||||
TYANMB=s27i35
|
TYANMB=s2735
|
||||||
cd "$TYANMB"
|
cd "$TYANMB"
|
||||||
make
|
make
|
||||||
#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
|
#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue