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mb/google/brya/var/taniks: Modify DPTF setting for taniks 

Adjust sensor trigger point and fan duty according to thermal team
tuning results.

BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng 2022-06-21 15:43:36 +08:00 committed by Martin L Roth
parent 4b5a98d8d5
commit ccfbfdf0bb
1 changed files with 27 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
src/mainboard/google/brya/variants/taniks/overridetree.cb
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@ -124,41 +124,41 @@ chip soc/intel/alderlake
[0] = { [0] = {
.target = DPTF_CPU, .target = DPTF_CPU,
.thresholds = { .thresholds = {
TEMP_PCT(85, 90), TEMP_PCT(60, 68),
TEMP_PCT(80, 74), TEMP_PCT(56, 50),
TEMP_PCT(75, 74), TEMP_PCT(52, 50),
TEMP_PCT(70, 74), TEMP_PCT(46, 40),
TEMP_PCT(65, 74), TEMP_PCT(42, 40),
} }
}, },
[1] = { [1] = {
.target = DPTF_TEMP_SENSOR_1, .target = DPTF_TEMP_SENSOR_1,
.thresholds = { .thresholds = {
TEMP_PCT(57, 70), TEMP_PCT(60, 68),
TEMP_PCT(54, 60), TEMP_PCT(56, 50),
TEMP_PCT(48, 60), TEMP_PCT(52, 50),
TEMP_PCT(45, 45), TEMP_PCT(46, 40),
TEMP_PCT(42, 39), TEMP_PCT(42, 40),
} }
}, },
[2] = { [2] = {
.target = DPTF_TEMP_SENSOR_2, .target = DPTF_TEMP_SENSOR_2,
.thresholds = { .thresholds = {
TEMP_PCT(57, 70), TEMP_PCT(60, 68),
TEMP_PCT(54, 60), TEMP_PCT(56, 50),
TEMP_PCT(48, 60), TEMP_PCT(52, 50),
TEMP_PCT(45, 45), TEMP_PCT(46, 40),
TEMP_PCT(42, 39), TEMP_PCT(42, 40),
} }
}, },
[3] = { [3] = {
.target = DPTF_TEMP_SENSOR_3, .target = DPTF_TEMP_SENSOR_3,
.thresholds = { .thresholds = {
TEMP_PCT(57, 70), TEMP_PCT(60, 69),
TEMP_PCT(54, 60), TEMP_PCT(56, 50),
TEMP_PCT(48, 60), TEMP_PCT(52, 50),
TEMP_PCT(45, 45), TEMP_PCT(46, 40),
TEMP_PCT(42, 39), TEMP_PCT(42, 40),
} }
} }
}" }"
@ -210,13 +210,13 @@ chip soc/intel/alderlake
register "controls.fan_perf" = "{ register "controls.fan_perf" = "{
[0] = { 100, 6000, 220, 2200, }, [0] = { 100, 6000, 220, 2200, },
[1] = { 92, 5500, 180, 1800, }, [1] = { 92, 5500, 180, 1800, },
[2] = { 85, 5000, 145, 1450, }, [2] = { 78, 4500, 145, 1450, },
[3] = { 70, 4400, 115, 1150, }, [3] = { 68, 3900, 115, 1150, },
[4] = { 60, 3900, 90, 900, }, [4] = { 60, 3600, 90, 900, },
[5] = { 45, 3300, 55, 550, }, [5] = { 50, 3200, 55, 550, },
[6] = { 39, 3000, 30, 300, }, [6] = { 40, 2800, 30, 300, },
[7] = { 33, 2900, 15, 150, }, [7] = { 33, 2500, 15, 150, },
[8] = { 10, 800, 10, 100, }, [8] = { 12, 800, 10, 100, },
[9] = { 0, 0, 0, 50, } [9] = { 0, 0, 0, 50, }
}" }"