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Intel FSP platforms: Fix timestamps 

Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.

Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This commit is contained in:
Kyösti Mälkki 2014-12-31 21:48:48 +02:00
parent 29d358e6a1
commit cd02ef19e5
3 changed files with 16 additions and 29 deletions
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23
src/mainboard/intel/cougar_canyon2/romstage.c
View File

@ -182,11 +182,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x40); post_code(0x40);
#if CONFIG_COLLECT_TIMESTAMPS timestamp_init(get_initial_timestamp());
uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); timestamp_add_now(TS_START_ROMSTAGE);
/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time);
#endif
pch_enable_lpc(); pch_enable_lpc();
@ -234,11 +231,7 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48); post_code(0x48);
#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_BEFORE_INITRAM);
uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4);
/* since this mainboard doesn't use audio, we can stuff the TSC values in there */
pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time);
#endif
/* /*
* Call early init to initialize memory and chipset. This function returns * Call early init to initialize memory and chipset. This function returns
@ -259,11 +252,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
u32 reg32; u32 reg32;
void *cbmem_hob_ptr; void *cbmem_hob_ptr;
#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_AFTER_INITRAM);
uint64_t after_initram_time = timestamp_get();
uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4;
uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4;
#endif
/* /*
* HD AUDIO is not used on this system, so we're using some registers * HD AUDIO is not used on this system, so we're using some registers
@ -317,10 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
*(u32*)cbmem_hob_ptr = (u32)HobListPtr; *(u32*)cbmem_hob_ptr = (u32)HobListPtr;
post_code(0x4f); post_code(0x4f);
timestamp_init(get_initial_timestamp());
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_initram_time );
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE); timestamp_add_now(TS_END_ROMSTAGE);
/* Load the ramstage. */ /* Load the ramstage. */

11
src/soc/intel/fsp_baytrail/romstage/romstage.c
View File

@ -160,6 +160,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x40); post_code(0x40);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses(); program_base_addresses();
post_code(0x41); post_code(0x41);
@ -198,6 +201,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x47); post_code(0x47);
timestamp_add_now(TS_BEFORE_INITRAM);
/* /*
* Call early init to initialize memory and chipset. This function returns * Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB * to the romstage_main_continue function with a pointer to the HOB
@ -219,9 +224,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
uint32_t prev_sleep_state; uint32_t prev_sleep_state;
struct romstage_handoff *handoff; struct romstage_handoff *handoff;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) timestamp_add_now(TS_AFTER_INITRAM);
uint64_t after_initram_time = timestamp_get();
#endif
post_code(0x4a); post_code(0x4a);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
@ -264,8 +267,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
else else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
timestamp_init(get_initial_timestamp());
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE); timestamp_add_now(TS_END_ROMSTAGE);
post_code(0x4f); post_code(0x4f);

11
src/southbridge/intel/fsp_rangeley/romstage.c
View File

@ -53,6 +53,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
*/ */
outb(0x40, 0x80); outb(0x40, 0x80);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* Rangeley UART POR state is enabled */ /* Rangeley UART POR state is enabled */
console_init(); console_init();
post_code(0x41); post_code(0x41);
@ -75,6 +78,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
read32(func_dis); read32(func_dis);
} }
timestamp_add_now(TS_BEFORE_INITRAM);
/* /*
* Call early init to initialize memory and chipset. This function returns * Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB * to the romstage_main_continue function with a pointer to the HOB
@ -94,9 +99,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
int cbmem_was_initted; int cbmem_was_initted;
void *cbmem_hob_ptr; void *cbmem_hob_ptr;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) timestamp_add_now(TS_AFTER_INITRAM);
uint64_t after_initram_time = timestamp_get();
#endif
post_code(0x48); post_code(0x48);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
@ -127,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e); post_code(0x4e);
timestamp_init(get_initial_timestamp());
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE); timestamp_add_now(TS_END_ROMSTAGE);
post_code(0x4f); post_code(0x4f);