soc/amd/stoneyridge: Simplify and fix SMBUS code
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c call functions within smbus.c. Fix some functions that wrongly use SMBHSTCTRL as the register for the data being transfered. The correct register is SMBHSTDAT0. Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c. BUG=b:62200225 Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Richard Spiegel
Aaron Durbin
parent
3f6c400310
commit
cd04e31c8b
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@ -27,8 +27,10 @@
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#define SMBHST_STAT_BUSY 0x01
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#define SMBHST_STAT_CLEAR 0xff
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#define SMBHST_STAT_NOERROR 0x02
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#define SMBHST_STAT_VAL_BITS 0x1f
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#define SMBHST_STAT_ERROR_BITS 0x1c
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#define SMBSLVSTAT 0x1
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#define SMBSLVSTAT 0x1
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#define SMBSLV_STAT_ALERT 0x20
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#define SMBSLV_STAT_SHADOW2 0x10
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#define SMBSLV_STAT_SHADOW1 0x08
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@ -60,6 +62,9 @@
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#define SMBSLVDAT 0xc
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#define SMBTIMING 0xe
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#define SMB_ASF_IO_BASE 0x01
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#define SMB_SPEED_400KHZ (66000000 / (400000 * 4))
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#define AX_INDXC 0
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#define AX_INDXP 2
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#define AXCFG 4
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@ -86,10 +91,10 @@
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#define rcindxp_reg(reg, port, mask, val) \
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alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
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int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
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int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
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int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
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int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
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int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val);
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int do_smbus_recv_byte(u16 smbus_io_base, u8 device);
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int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val);
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void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
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void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
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void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
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@ -48,7 +48,7 @@ static void sm_init(device_t dev)
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static int lsmbus_recv_byte(device_t dev)
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{
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u32 device;
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u8 device;
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struct resource *res;
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struct bus *pbus;
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@ -62,7 +62,7 @@ static int lsmbus_recv_byte(device_t dev)
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static int lsmbus_send_byte(device_t dev, u8 val)
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{
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u32 device;
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u8 device;
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struct resource *res;
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struct bus *pbus;
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@ -76,7 +76,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
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static int lsmbus_read_byte(device_t dev, u8 address)
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{
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u32 device;
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u8 device;
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struct resource *res;
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struct bus *pbus;
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@ -90,7 +90,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
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static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
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{
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u32 device;
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u8 device;
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struct resource *res;
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struct bus *pbus;
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@ -108,20 +108,12 @@ static struct smbus_bus_operations lops_smbus_bus = {
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.write_byte = lsmbus_write_byte,
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};
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static void sm_read_resources(device_t dev)
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{
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}
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static void sm_set_resources(struct device *dev)
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{
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations smbus_ops = {
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.read_resources = sm_read_resources,
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.set_resources = sm_set_resources,
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = pci_dev_enable_resources,
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.init = sm_init,
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.scan_bus = scan_smbus,
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@ -17,14 +17,14 @@
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#include <stdint.h>
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#include <soc/smbus.h>
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static int smbus_wait_until_ready(u32 smbus_io_base)
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static int smbus_wait_until_ready(u16 smbus_io_base)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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u8 val;
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val = inb(smbus_io_base + SMBHSTSTAT);
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val &= 0x1f;
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val &= SMBHST_STAT_VAL_BITS;
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if (val == 0) { /* ready now */
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return 0;
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}
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@ -33,7 +33,7 @@ static int smbus_wait_until_ready(u32 smbus_io_base)
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return -2; /* time out */
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}
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static int smbus_wait_until_done(u32 smbus_io_base)
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static int smbus_wait_until_done(u16 smbus_io_base)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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@ -41,10 +41,10 @@ static int smbus_wait_until_done(u32 smbus_io_base)
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u8 val;
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val = inb(smbus_io_base + SMBHSTSTAT);
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val &= 0x1f; /* mask off reserved bits */
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if (val & 0x1c)
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val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */
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if (val & SMBHST_STAT_ERROR_BITS)
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return -5; /* error */
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if (val == 0x02) {
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if (val == SMBHST_STAT_NOERROR) {
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outb(val, smbus_io_base + SMBHSTSTAT); /* clear sts */
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return 0;
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}
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@ -52,7 +52,7 @@ static int smbus_wait_until_done(u32 smbus_io_base)
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return -3; /* timeout */
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}
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int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
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int do_smbus_recv_byte(u16 smbus_io_base, u8 device)
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{
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u8 byte;
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@ -63,8 +63,8 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
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outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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byte = inb(smbus_io_base + SMBHSTCTRL);
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byte &= 0xe3; /* Clear [4:2] */
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byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start the command */
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
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outb(byte, smbus_io_base + SMBHSTCTRL);
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/* poll for transaction completion */
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@ -72,12 +72,12 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
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return -3; /* timeout or error */
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/* read results of transaction */
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byte = inb(smbus_io_base + SMBHSTCMD);
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byte = inb(smbus_io_base + SMBHSTDAT0);
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return byte;
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}
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int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
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int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val)
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{
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u8 byte;
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@ -85,14 +85,14 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
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return -2; /* not ready */
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/* set the command... */
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outb(val, smbus_io_base + SMBHSTCMD);
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outb(val, smbus_io_base + SMBHSTDAT0);
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/* set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
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byte = inb(smbus_io_base + SMBHSTCTRL);
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byte &= 0xe3; /* Clear [4:2] */
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byte |= (1 << 2) | (1 << 6); /* Byte data R/W cmd, start command */
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
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outb(byte, smbus_io_base + SMBHSTCTRL);
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/* poll for transaction completion */
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@ -102,8 +102,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
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return 0;
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}
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int do_smbus_read_byte(u32 smbus_io_base, u32 device,
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u32 address)
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int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
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{
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u8 byte;
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@ -117,8 +116,8 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device,
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outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
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byte = inb(smbus_io_base + SMBHSTCTRL);
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byte &= 0xe3; /* Clear [4:2] */
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byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
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outb(byte, smbus_io_base + SMBHSTCTRL);
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/* poll for transaction completion */
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@ -131,8 +130,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device,
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return byte;
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}
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int do_smbus_write_byte(u32 smbus_io_base, u32 device,
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u32 address, u8 val)
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int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val)
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{
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u8 byte;
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@ -149,8 +147,8 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device,
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outb(val, smbus_io_base + SMBHSTDAT0);
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byte = inb(smbus_io_base + SMBHSTCTRL);
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byte &= 0xe3; /* Clear [4:2] */
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byte |= (1 << 3) | (1 << 6); /* Byte data R/W cmd, start command */
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
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outb(byte, smbus_io_base + SMBHSTCTRL);
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/* poll for transaction completion */
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@ -160,8 +158,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device,
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return 0;
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}
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void alink_ab_indx(u32 reg_space, u32 reg_addr,
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u32 mask, u32 val)
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void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
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{
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u32 tmp;
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@ -185,8 +182,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr,
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outl(0, AB_INDX);
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}
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void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
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u32 mask, u32 val)
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void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
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{
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u32 tmp;
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@ -210,7 +206,8 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
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outl(0, AB_INDX);
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}
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/* space = 0: AX_INDXC, AX_DATAC
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/*
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* space = 0: AX_INDXC, AX_DATAC
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* space = 1: AX_INDXP, AX_DATAP
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*/
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void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
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@ -23,72 +23,6 @@
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#include <soc/smbus.h>
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#include <dimmSpd.h>
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/*
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* readSmbusByteData - read a single SPD byte from any offset
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*/
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static int readSmbusByteData(int iobase, int address, char *buffer, int offset)
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{
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unsigned int status;
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UINT64 limit;
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address |= 1; // set read bit
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__outbyte(iobase + SMBHSTSTAT, SMBHST_STAT_CLEAR);
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__outbyte(iobase + SMBSLVSTAT, SMBSLV_STAT_CLEAR);
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__outbyte(iobase + SMBHSTCMD, offset); // offset in eeprom
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__outbyte(iobase + SMBHSTADDR, address); // slave addr & read bit
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__outbyte(iobase + SMBHSTCTRL, SMBHST_CTRL_STRT + SMBHST_CTRL_BDT_RW);
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// time limit to avoid hanging for unexpected error status
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limit = __rdtsc() + 2000000000 / 10;
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for (;;) {
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status = __inbyte(iobase + SMBHSTSTAT);
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if (__rdtsc() > limit)
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break;
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if ((status & SMBHST_STAT_INTERRUPT) == 0)
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continue; // SMBusInterrupt not set, keep waiting
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if ((status & SMBHST_STAT_BUSY) == SMBHST_STAT_BUSY)
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continue; // HostBusy set, keep waiting
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break;
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}
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buffer[0] = __inbyte(iobase + SMBHSTDAT0);
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if (status == SMBHST_STAT_NOERROR)
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status = 0; // done with no errors
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return status;
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}
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/*
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* readSmbusByte - read a single SPD byte from the default offset
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* this function is faster function readSmbusByteData
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*/
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static int readSmbusByte(int iobase, int address, char *buffer)
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{
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unsigned int status;
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UINT64 limit;
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__outbyte(iobase + SMBHSTSTAT, SMBHST_STAT_CLEAR);
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__outbyte(iobase + SMBHSTCTRL, SMBHST_CTRL_STRT + SMBHST_CTRL_BTE_RW);
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// time limit to avoid hanging for unexpected error status
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limit = __rdtsc() + 2000000000 / 10;
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for (;;) {
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status = __inbyte(iobase + SMBHSTSTAT);
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if (__rdtsc() > limit)
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break;
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if ((status & SMBHST_STAT_INTERRUPT) == 0)
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continue; // SMBusInterrupt not set, keep waiting
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if ((status & SMBHST_STAT_BUSY) == SMBHST_STAT_BUSY)
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continue; // HostBusy set, keep waiting
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break;
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}
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buffer[0] = __inbyte(iobase + SMBHSTDAT0);
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if (status == SMBHST_STAT_NOERROR)
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status = 0; // done with no errors
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return status;
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}
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/*
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* readspd - Read one or more SPD bytes from a DIMM.
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* Start with offset zero and read sequentially.
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@ -96,29 +30,43 @@ static int readSmbusByte(int iobase, int address, char *buffer)
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* sending offset for every byte.
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* Reads 128 bytes in 7-8 ms at 400 KHz.
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*/
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static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count)
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static int readspd(uint16_t iobase, int SmbusSlaveAddress,
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char *buffer, size_t count)
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{
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int index, error;
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u8 dev_addr;
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size_t index;
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int error;
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char *pbuf = buffer;
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printk(BIOS_SPEW, "-------------READING SPD-----------\n");
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printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n",
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iobase, SmbusSlaveAddress, count);
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iobase, SmbusSlaveAddress, (int)count);
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/* read the first byte using offset zero */
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error = readSmbusByteData(iobase, SmbusSlaveAddress, buffer, 0);
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/*
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* Convert received device address to the format accepted by
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* do_smbus_read_byte and do_smbus_recv_byte.
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*/
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dev_addr = (SmbusSlaveAddress >> 1);
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if (error) {
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/* Read the first SPD byte */
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error = do_smbus_read_byte(iobase, dev_addr, 0);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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} else {
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*pbuf = (char) error;
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pbuf++;
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}
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/* read the remaining bytes using auto-increment for speed */
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for (index = 1; index < count; index++) {
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error = readSmbusByte(iobase, SmbusSlaveAddress,
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&buffer[index]);
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if (error) {
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/* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
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for (index = 1 ; index < count ; index++) {
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error = do_smbus_recv_byte(iobase, dev_addr);
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if (error < 0) {
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printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
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return error;
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} else {
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*pbuf = (char) error;
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pbuf++;
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}
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}
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printk(BIOS_SPEW, "\n");
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@ -129,22 +77,22 @@ static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count)
|
|||
|
||||
static void writePmReg(int reg, int data)
|
||||
{
|
||||
__outbyte(PM_INDEX, reg);
|
||||
__outbyte(PM_DATA, data);
|
||||
outb(reg, PM_INDEX);
|
||||
outb(data, PM_DATA);
|
||||
}
|
||||
|
||||
static void setupFch(int ioBase)
|
||||
static void setupFch(uint16_t ioBase)
|
||||
{
|
||||
/* register 0x2c and 0x2d are not defined in public datasheet */
|
||||
writePmReg(0x2d, ioBase >> 8);
|
||||
writePmReg(0x2c, ioBase | 1);
|
||||
/* set SMBus clock to 400 KHz */
|
||||
__outbyte(ioBase + SMBTIMING, 66000000 / 400000 / 4);
|
||||
writePmReg(SMB_ASF_IO_BASE, ioBase >> 8);
|
||||
outb(SMB_SPEED_400KHZ, ioBase + SMBTIMING);
|
||||
/* Clear all SMBUS status bits */
|
||||
outb(SMBHST_STAT_CLEAR, ioBase + SMBHSTSTAT);
|
||||
outb(SMBSLV_STAT_CLEAR, ioBase + SMBSLVSTAT);
|
||||
}
|
||||
|
||||
int sb_readSpd(int spdAddress, char *buf, size_t len)
|
||||
{
|
||||
int ioBase = SMB_BASE_ADDR;
|
||||
uint16_t ioBase = SMB_BASE_ADDR;
|
||||
setupFch(ioBase);
|
||||
return readspd(ioBase, spdAddress, buf, len);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <cbmem.h>
|
||||
#include <amd_pci_util.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <soc/smbus.h>
|
||||
#include <soc/smi.h>
|
||||
#include <fchec.h>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue