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mb/google/brya/var/taeko: Enable CsPiStartHighinEct 

Enable CsPiStartHighinEct to fix MRC Cache fail issue

BUG=b:279835630
BRANCH=none
TEST=Pass MRC Cache test with toolkit 1000 times

Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Joey Peng 2023-06-17 09:30:04 +08:00 committed by Nick Vaccaro
parent 41b92fef81
commit cd1006cb0e
1 changed files with 73 additions and 1 deletions
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74
src/mainboard/google/brya/variants/taeko/memory.c
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@ -2,7 +2,10 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <gpio.h>
#include <memory_info.h>
#include <string.h>
static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP4X,
@ -66,9 +69,78 @@ static const struct mb_cfg baseboard_memcfg = {
.ect = 1, /* Enable Early Command Training */
};
static const struct mb_cfg hynix_memconfig = {
.type = MEM_TYPE_LP4X,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {40, 30, 30, 30, 30},
},
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, },
.dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, },
},
.ddr1 = {
.dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, },
.dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, },
},
.ddr2 = {
.dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, },
.dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, },
},
.ddr3 = {
.dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, },
.dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, },
},
.ddr4 = {
.dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, },
.dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, },
},
.ddr5 = {
.dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, },
.dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, },
},
.ddr6 = {
.dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, },
.dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, },
},
.ddr7 = {
.dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, },
.dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, },
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},
.ect = 1, /* Enable Early Command Training */
.cs_pi_start_high_in_ect = 1,
};
const struct mb_cfg *variant_memory_params(void)
{
return &baseboard_memcfg;
const char *dram_part_num = mainboard_get_dram_part_num();
if (strcmp(dram_part_num, "H54G46CYRBX267N") == 0) {
printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix DRAM part\n");
return &hynix_memconfig;
} else {
return &baseboard_memcfg;
}
}
int variant_memory_sku(void)