AMD Fam15tn boards: Document lane ID mapping from BKDG
To make it easier to fill in the values, place the table from the BIOS and Kernel Developer’s Guide (BKDG) [1] as a comment. [1] http://www.coreboot.org/Datasheets#AMD_Fam15 Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3221 Tested-by: build bot (Jenkins)
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Rudolf Marek
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38c326d041
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cd1cef4438
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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* Lane Id
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* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
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* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
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* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
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* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
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* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
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* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
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* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
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* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
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* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
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* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
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* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
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* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
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* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
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* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
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* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
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* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
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* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
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* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
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* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
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* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
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* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
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* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
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* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
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* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
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* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
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* 25 DP0_TX[P,N]1
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* 26 DP0_TX[P,N]2
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* 27 DP0_TX[P,N]3
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* 28 DP1_TX[P,N]0
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* 29 DP1_TX[P,N]1
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* 30 DP1_TX[P,N]2
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* 31 DP1_TX[P,N]3
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* 32 DP2_TX[P,N]0
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* 33 DP2_TX[P,N]1
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* 34 DP2_TX[P,N]2
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* 35 DP2_TX[P,N]3
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* 36 DP2_TX[P,N]4
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* 37 DP2_TX[P,N]5
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* 38 DP2_TX[P,N]6
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*/
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PCIe_PORT_DESCRIPTOR PortList [] = {
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/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
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{
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@ -26,6 +26,51 @@
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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* Lane Id
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* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
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* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
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* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
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* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
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* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
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* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
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* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
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* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
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* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
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* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
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* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
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* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
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* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
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* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
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* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
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* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
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* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
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* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
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* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
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* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
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* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
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* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
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* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
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* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
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* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
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* 25 DP0_TX[P,N]1
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* 26 DP0_TX[P,N]2
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* 27 DP0_TX[P,N]3
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* 28 DP1_TX[P,N]0
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* 29 DP1_TX[P,N]1
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* 30 DP1_TX[P,N]2
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* 31 DP1_TX[P,N]3
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* 32 DP2_TX[P,N]0
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* 33 DP2_TX[P,N]1
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* 34 DP2_TX[P,N]2
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* 35 DP2_TX[P,N]3
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* 36 DP2_TX[P,N]4
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* 37 DP2_TX[P,N]5
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* 38 DP2_TX[P,N]6
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*/
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PCIe_PORT_DESCRIPTOR PortList [] = {
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/* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
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{
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@ -26,6 +26,51 @@
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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* Lane Id
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* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
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* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
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* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
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* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
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* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
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* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
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* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
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* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
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* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
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* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
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* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
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* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
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* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
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* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
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* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
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* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
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* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
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* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
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* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
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* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
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* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
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* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
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* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
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* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
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* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
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* 25 DP0_TX[P,N]1
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* 26 DP0_TX[P,N]2
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* 27 DP0_TX[P,N]3
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* 28 DP1_TX[P,N]0
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* 29 DP1_TX[P,N]1
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* 30 DP1_TX[P,N]2
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* 31 DP1_TX[P,N]3
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* 32 DP2_TX[P,N]0
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* 33 DP2_TX[P,N]1
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* 34 DP2_TX[P,N]2
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* 35 DP2_TX[P,N]3
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* 36 DP2_TX[P,N]4
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* 37 DP2_TX[P,N]5
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* 38 DP2_TX[P,N]6
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*/
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PCIe_PORT_DESCRIPTOR PortList [] = {
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/* PCIe port, Lanes 8:23, PCI Device Number 2 */
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{
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