devicetree: Remove duplicate chip_ops declarations

These are only referenced inside auto-generated static.c
files, and util/sconfig also generates the declarations
automatically from source file pathnames.

Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-18 16:33:06 +03:00
parent 216f717d31
commit cd2aa47a34
16 changed files with 0 additions and 44 deletions

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@ -13,8 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
extern struct chip_operations cpu_intel_haswell_ops;
/* Magic value used to locate this chip in the device tree */ /* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC #define SPEEDSTEP_APIC_MAGIC 0xACAC

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@ -17,11 +17,6 @@
#ifndef _EC_COMPAL_ENE932_CHIP_H #ifndef _EC_COMPAL_ENE932_CHIP_H
#define _EC_COMPAL_ENE932_CHIP_H #define _EC_COMPAL_ENE932_CHIP_H
#include <device/device.h>
struct chip_operations;
extern struct chip_operations ec_compal_ene932_ops;
struct ec_compal_ene932_config { struct ec_compal_ene932_config {
}; };

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@ -16,9 +16,6 @@
#ifndef EC_GOOGLE_CHROMEEC_CHIP_H #ifndef EC_GOOGLE_CHROMEEC_CHIP_H
#define EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H
#include <device/device.h>
extern struct chip_operations ec_google_chromeec_ops;
struct ec_google_chromeec_config { struct ec_google_chromeec_config {
}; };

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@ -16,10 +16,6 @@
#ifndef EC_GOOGLE_WILCO_CHIP_H #ifndef EC_GOOGLE_WILCO_CHIP_H
#define EC_GOOGLE_WILCO_CHIP_H #define EC_GOOGLE_WILCO_CHIP_H
#include <device/device.h>
extern struct chip_operations ec_google_wilco_ops;
struct ec_google_wilco_config { struct ec_google_wilco_config {
}; };

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@ -17,11 +17,6 @@
#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H #ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
#define _EC_QUANTA_ENE_KB3940Q_CHIP_H #define _EC_QUANTA_ENE_KB3940Q_CHIP_H
#include <device/device.h>
struct chip_operations;
extern struct chip_operations ec_quanta_ene_kb3940q_ops;
struct ec_quanta_ene_kb3940q_config { struct ec_quanta_ene_kb3940q_config {
}; };

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@ -17,11 +17,6 @@
#ifndef _EC_QUANTA_IT8518_CHIP_H #ifndef _EC_QUANTA_IT8518_CHIP_H
#define _EC_QUANTA_IT8518_CHIP_H #define _EC_QUANTA_IT8518_CHIP_H
#include <device/device.h>
struct chip_operations;
extern struct chip_operations ec_quanta_it8518_ops;
struct ec_quanta_it8518_config { struct ec_quanta_it8518_config {
}; };

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@ -16,11 +16,6 @@
#ifndef _EC_RODA_IT8518_CHIP_H #ifndef _EC_RODA_IT8518_CHIP_H
#define _EC_RODA_IT8518_CHIP_H #define _EC_RODA_IT8518_CHIP_H
#include <device/device.h>
struct chip_operations;
extern struct chip_operations ec_roda_it8518_ops;
struct ec_roda_it8518_config { struct ec_roda_it8518_config {
u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */
}; };

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@ -45,6 +45,4 @@ struct northbridge_intel_haswell_config {
struct i915_gpu_controller_info gfx; struct i915_gpu_controller_info gfx;
}; };
extern struct chip_operations northbridge_intel_haswell_ops;
#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */

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@ -87,5 +87,4 @@ struct soc_intel_baytrail_config {
int disable_ddr_2x_refresh_rate; int disable_ddr_2x_refresh_rate;
}; };
extern struct chip_operations soc_intel_baytrail_ops;
#endif /* _BAYTRAIL_CHIP_H_ */ #endif /* _BAYTRAIL_CHIP_H_ */

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@ -171,6 +171,4 @@ struct soc_intel_braswell_config {
UINT8 I2C6Frequency; UINT8 I2C6Frequency;
}; };
extern struct chip_operations soc_intel_braswell_ops;
#endif /* _SOC_CHIP_H_ */ #endif /* _SOC_CHIP_H_ */

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@ -164,6 +164,4 @@ struct soc_intel_broadwell_config {
typedef struct soc_intel_broadwell_config config_t; typedef struct soc_intel_broadwell_config config_t;
extern struct chip_operations soc_ops;
#endif #endif

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@ -72,8 +72,6 @@ struct soc_intel_denverton_ns_config {
uint32_t ipc3; uint32_t ipc3;
}; };
extern struct chip_operations soc_intel_denverton_ns_ops;
typedef struct soc_intel_denverton_ns_config config_t; typedef struct soc_intel_denverton_ns_config config_t;
#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */ #endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */

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@ -353,5 +353,4 @@ struct soc_intel_fsp_baytrail_config {
}; };
extern struct chip_operations soc_intel_fsp_baytrail_ops;
#endif /* _FSP_BAYTRAIL_CHIP_H_ */ #endif /* _FSP_BAYTRAIL_CHIP_H_ */

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@ -29,5 +29,4 @@ struct soc_intel_fsp_broadwell_de_config {
typedef struct soc_intel_fsp_broadwell_de_config config_t; typedef struct soc_intel_fsp_broadwell_de_config config_t;
extern struct chip_operations soc_intel_fsp_broadwell_de_ops;
#endif /* _SOC_CHIP_H_ */ #endif /* _SOC_CHIP_H_ */

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@ -113,6 +113,4 @@ struct soc_intel_quark_config {
uint8_t SmmTsegSize; /* SMM size in MiB */ uint8_t SmmTsegSize; /* SMM size in MiB */
}; };
extern struct chip_operations soc_ops;
#endif #endif

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@ -591,6 +591,4 @@ struct soc_intel_skylake_config {
typedef struct soc_intel_skylake_config config_t; typedef struct soc_intel_skylake_config config_t;
extern struct chip_operations soc_ops;
#endif #endif