devicetree: Remove duplicate chip_ops declarations
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,8 +13,6 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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extern struct chip_operations cpu_intel_haswell_ops;
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/* Magic value used to locate this chip in the device tree */
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/* Magic value used to locate this chip in the device tree */
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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@ -17,11 +17,6 @@
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#ifndef _EC_COMPAL_ENE932_CHIP_H
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#ifndef _EC_COMPAL_ENE932_CHIP_H
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#define _EC_COMPAL_ENE932_CHIP_H
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#define _EC_COMPAL_ENE932_CHIP_H
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#include <device/device.h>
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struct chip_operations;
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extern struct chip_operations ec_compal_ene932_ops;
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struct ec_compal_ene932_config {
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struct ec_compal_ene932_config {
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};
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};
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@ -16,9 +16,6 @@
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#ifndef EC_GOOGLE_CHROMEEC_CHIP_H
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#ifndef EC_GOOGLE_CHROMEEC_CHIP_H
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#define EC_GOOGLE_CHROMEEC_CHIP_H
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#define EC_GOOGLE_CHROMEEC_CHIP_H
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#include <device/device.h>
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extern struct chip_operations ec_google_chromeec_ops;
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struct ec_google_chromeec_config {
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struct ec_google_chromeec_config {
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};
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};
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@ -16,10 +16,6 @@
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#ifndef EC_GOOGLE_WILCO_CHIP_H
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#ifndef EC_GOOGLE_WILCO_CHIP_H
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#define EC_GOOGLE_WILCO_CHIP_H
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#define EC_GOOGLE_WILCO_CHIP_H
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#include <device/device.h>
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extern struct chip_operations ec_google_wilco_ops;
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struct ec_google_wilco_config {
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struct ec_google_wilco_config {
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};
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};
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@ -17,11 +17,6 @@
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#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
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#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
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#define _EC_QUANTA_ENE_KB3940Q_CHIP_H
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#define _EC_QUANTA_ENE_KB3940Q_CHIP_H
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#include <device/device.h>
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struct chip_operations;
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extern struct chip_operations ec_quanta_ene_kb3940q_ops;
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struct ec_quanta_ene_kb3940q_config {
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struct ec_quanta_ene_kb3940q_config {
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};
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};
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@ -17,11 +17,6 @@
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#ifndef _EC_QUANTA_IT8518_CHIP_H
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#ifndef _EC_QUANTA_IT8518_CHIP_H
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#define _EC_QUANTA_IT8518_CHIP_H
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#define _EC_QUANTA_IT8518_CHIP_H
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#include <device/device.h>
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struct chip_operations;
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extern struct chip_operations ec_quanta_it8518_ops;
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struct ec_quanta_it8518_config {
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struct ec_quanta_it8518_config {
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};
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};
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@ -16,11 +16,6 @@
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#ifndef _EC_RODA_IT8518_CHIP_H
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#ifndef _EC_RODA_IT8518_CHIP_H
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#define _EC_RODA_IT8518_CHIP_H
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#define _EC_RODA_IT8518_CHIP_H
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#include <device/device.h>
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struct chip_operations;
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extern struct chip_operations ec_roda_it8518_ops;
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struct ec_roda_it8518_config {
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struct ec_roda_it8518_config {
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u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */
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u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */
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};
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};
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@ -45,6 +45,4 @@ struct northbridge_intel_haswell_config {
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struct i915_gpu_controller_info gfx;
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struct i915_gpu_controller_info gfx;
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};
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};
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extern struct chip_operations northbridge_intel_haswell_ops;
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#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */
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#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */
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@ -87,5 +87,4 @@ struct soc_intel_baytrail_config {
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int disable_ddr_2x_refresh_rate;
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int disable_ddr_2x_refresh_rate;
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};
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};
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extern struct chip_operations soc_intel_baytrail_ops;
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#endif /* _BAYTRAIL_CHIP_H_ */
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#endif /* _BAYTRAIL_CHIP_H_ */
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@ -171,6 +171,4 @@ struct soc_intel_braswell_config {
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UINT8 I2C6Frequency;
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UINT8 I2C6Frequency;
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};
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};
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extern struct chip_operations soc_intel_braswell_ops;
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#endif /* _SOC_CHIP_H_ */
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#endif /* _SOC_CHIP_H_ */
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@ -164,6 +164,4 @@ struct soc_intel_broadwell_config {
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typedef struct soc_intel_broadwell_config config_t;
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typedef struct soc_intel_broadwell_config config_t;
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extern struct chip_operations soc_ops;
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#endif
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#endif
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@ -72,8 +72,6 @@ struct soc_intel_denverton_ns_config {
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uint32_t ipc3;
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uint32_t ipc3;
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};
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};
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extern struct chip_operations soc_intel_denverton_ns_ops;
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typedef struct soc_intel_denverton_ns_config config_t;
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typedef struct soc_intel_denverton_ns_config config_t;
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#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */
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#endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */
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@ -353,5 +353,4 @@ struct soc_intel_fsp_baytrail_config {
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};
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};
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extern struct chip_operations soc_intel_fsp_baytrail_ops;
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#endif /* _FSP_BAYTRAIL_CHIP_H_ */
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#endif /* _FSP_BAYTRAIL_CHIP_H_ */
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@ -29,5 +29,4 @@ struct soc_intel_fsp_broadwell_de_config {
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typedef struct soc_intel_fsp_broadwell_de_config config_t;
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typedef struct soc_intel_fsp_broadwell_de_config config_t;
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extern struct chip_operations soc_intel_fsp_broadwell_de_ops;
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#endif /* _SOC_CHIP_H_ */
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#endif /* _SOC_CHIP_H_ */
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@ -113,6 +113,4 @@ struct soc_intel_quark_config {
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uint8_t SmmTsegSize; /* SMM size in MiB */
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uint8_t SmmTsegSize; /* SMM size in MiB */
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};
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};
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extern struct chip_operations soc_ops;
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#endif
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#endif
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@ -591,6 +591,4 @@ struct soc_intel_skylake_config {
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typedef struct soc_intel_skylake_config config_t;
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typedef struct soc_intel_skylake_config config_t;
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extern struct chip_operations soc_ops;
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#endif
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#endif
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