soc/amd/picasso: Extract reset flags from northbridge.h

These are not northbridge functions.

BUG=b:147042464

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/cpu.c

@@ -12,7 +12,7 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
+#include <soc/reset.h>
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>

src/soc/amd/picasso/include/soc/reset.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __PI_PICASSO_RESET_H__
+#define __PI_PICASSO_RESET_H__
+
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
+
+#endif /* __PI_PICASSO_RESET_H__ */

src/soc/amd/picasso/mca.c

@@ -3,7 +3,7 @@
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
+#include <soc/reset.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>

src/soc/amd/picasso/reset.c

@@ -2,8 +2,8 @@
 
 #include <arch/io.h>
 #include <reset.h>
-#include <soc/northbridge.h>
 #include <soc/pci_devs.h>
+#include <soc/reset.h>
 #include <device/pci_ops.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>