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mb/google/nissa: Lock gpio pins for nissa variants 

There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.

BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
This commit is contained in:
Eric Lai 2022-07-01 13:51:39 +08:00 committed by Felix Held
parent 1b44c81d3d
commit cd4264fbe7
3 changed files with 17 additions and 17 deletions
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4
src/mainboard/google/brya/variants/craask/gpio.c
View File

@ -12,9 +12,9 @@ static const struct pad_config override_gpio_table[] = {
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
/* F12 : WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
};
/* Early pad configuration in bootblock */

10
src/mainboard/google/brya/variants/nereid/gpio.c
View File

@ -13,16 +13,16 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* B5 : SOC_I2C_SUB_SDA */
PAD_NC(GPP_B5, NONE),
PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
/* B6 : SOC_I2C_SUB_SCL */
PAD_NC(GPP_B6, NONE),
PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
/* D3 : WCAM_RST_L */
PAD_NC(GPP_D3, NONE),
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D15 : EN_PP2800_WCAM_X */
PAD_NC(GPP_D15, NONE),
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : EN_PP1800_PP1200_WCAM_X */
PAD_NC(GPP_D16, NONE),
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* H22 : WCAM_MCLK_R */
PAD_NC(GPP_H22, NONE),

20
src/mainboard/google/brya/variants/nivviks/gpio.c
View File

@ -13,9 +13,9 @@ static const struct pad_config board_id0_overrides[] = {
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
/* F12 : WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
/* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */
@ -45,29 +45,29 @@ static const struct pad_config override_gpio_table[] = {
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
/* F12 : WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
};
/* Pad configuration in ramstage for nirwen */
static const struct pad_config override_gpio_table_nirwen[] = {
/* B4 : SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
/* D11 : EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
/* E13 : SRCCLKREQ1# ==> WWAN_EN */
PAD_CFG_GPO(GPP_E13, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG),
/* E17 : SSD_PLN_L */
PAD_CFG_GPO(GPP_E17, 1, PLTRST),
PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
/* F12 : WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
};
/* Early pad configuration in bootblock for nivviks */