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exynos5/snow: remove wait_ms arg from dp_controller_init() 

This removes the wait_ms argument from the dp_controller_init(). The
only delay involved is a constant 60ms delay that happens if
everything else goes well. This delay is derived from the LCD spec
so there's no reason it should be baked into the controller code.

(This patch also has the side-effect of fixing a bug where we were
delaying on an undefined value for wait_ms).

Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3078
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-04-12 16:02:44 -07:00 committed by Ronald G. Minnich
parent c0b972f60d
commit cd4c8c1e0e
3 changed files with 15 additions and 18 deletions
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11
src/cpu/samsung/exynos5-common/exynos-fb.c
View File

@ -505,7 +505,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
/*
* Initialize DP display
*/
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
int dp_controller_init(struct s5p_dp_device *dp_device)
{
int ret;
struct s5p_dp_device *dp = dp_device;
@ -561,15 +561,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
return ret;
}
/*
* This delay is T3 in the LCD timing spec (defined as >200ms). We set
* this down to 60ms since that's the approximate maximum amount of time
* it'll take a bridge to start outputting LVDS data. The delay of
* >200ms is just a conservative value to avoid turning on the backlight
* when there's random LCD data on the screen. Shaving 140ms off the
* boot is an acceptable trade-off.
*/
*wait_ms = 60;
return 0;
}

2
src/cpu/samsung/exynos5-common/s5p-dp-core.h
View File

@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
int dp_controller_init(struct s5p_dp_device *dp_device);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
#endif /* _S5P_DP_CORE_H */

20
src/mainboard/google/snow/ramstage.c
View File

@ -139,6 +139,16 @@ static void exynos_dp_reset(void)
udelay(300 * 1000);
}
/*
* This delay is T3 in the LCD timing spec (defined as >200ms). We set
* this down to 60ms since that's the approximate maximum amount of time
* it'll take a bridge to start outputting LVDS data. The delay of
* >200ms is just a conservative value to avoid turning on the backlight
* when there's random LCD data on the screen. Shaving 140ms off the
* boot is an acceptable trade-off.
*/
#define LCD_T3_DELAY_MS 60
#define LCD_T5_DELAY_MS 10
#define LCD_T6_DELAY_MS 10
@ -199,7 +209,6 @@ static struct video_info snow_dp_video_info = {
static void mainboard_init(device_t dev)
{
int dp_tries;
unsigned int wait_ms;
struct s5p_dp_device dp_device = {
.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
.video_info = &snow_dp_video_info,
@ -215,20 +224,17 @@ static void mainboard_init(device_t dev)
exynos_dp_bridge_setup();
for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
if (wait_ms) {
udelay(wait_ms);
wait_ms = 0;
}
exynos_dp_bridge_init();
if (exynos_dp_hotplug()) {
exynos_dp_reset();
continue;
}
if (dp_controller_init(&dp_device, &wait_ms))
if (dp_controller_init(&dp_device))
continue;
udelay(LCD_T3_DELAY_MS * 1000);
snow_backlight_vdd();
snow_backlight_pwm();
snow_backlight_en();