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mb/intel: Get rid of whitespace before tab 

Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-05-28 13:35:35 +02:00 committed by Patrick Georgi
parent 60d7348a36
commit cd5f2b500d
11 changed files with 60 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/baskingridge/acpi/superio.asl
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@ -24,7 +24,7 @@
#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60

14
src/mainboard/intel/bayleybay_fsp/irqroute.h
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@ -20,14 +20,14 @@
#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
/*
*IR02h GFX INT(A) - PIRQ A
*IR02h GFX INT(A) - PIRQ A
*IR10h EMMC INT(ABCD) - PIRQ DEFG
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
*IR17h MMC INT(A) - PIRQ F
*IR11h SDIO INT(A) - PIRQ B
*IR12h SD INT(A) - PIRQ C
*IR13h SATA INT(A) - PIRQ D
*IR14h XHCI INT(A) - PIRQ E
*IR15h LP Audio INT(A) - PIRQ F
*IR17h MMC INT(A) - PIRQ F
*IR18h SIO INT(ABCD) - PIRQ BADC
*IR1Ah TXE INT(A) - PIRQ F
*IR1Bh HD Audio INT(A) - PIRQ G

2
src/mainboard/intel/d945gclf/acpi/thermal.asl
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@ -36,7 +36,7 @@ Scope (\_TZ)
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// Return (0xf5c)
// }
// Critical shutdown temperature

20
src/mainboard/intel/d945gclf/devicetree.cb
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@ -54,19 +54,19 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge

2
src/mainboard/intel/dg41wv/devicetree.cb
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@ -154,7 +154,7 @@ chip northbridge/intel/x4x # Northbridge
end
end
end
device pci 1f.1 off end # PATA/IDE
device pci 1f.1 off end # PATA/IDE
device pci 1f.2 on # SATA
subsystemid 0x8086 0x5756
end

2
src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
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@ -32,7 +32,7 @@ Method(_PRT)
/* ?? */
Package() { 0x0016ffff, 0, 0, 0x12 },
Package() { 0x0016ffff, 1, 0, 0x13 },
/* GBE 0:19.0 */
/* GBE 0:19.0 */
Package() { 0x0019ffff, 0, 0, 0x10 },
/* USB and EHCI */
Package() { 0x001affff, 0, 0, 0x10 },

2
src/mainboard/intel/emeraldlake2/acpi/superio.asl
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@ -24,7 +24,7 @@
#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60

38
src/mainboard/intel/kunimitsu/gpio.h
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@ -81,15 +81,15 @@ static const struct pad_config gpio_table[] = {
/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),
/* GYRO_INT */ PAD_CFG_NC(GPP_A22),
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),
@ -100,10 +100,10 @@ static const struct pad_config gpio_table[] = {
/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),
/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
@ -111,10 +111,10 @@ static const struct pad_config gpio_table[] = {
/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),
/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),
/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),
/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),
/* SML0DATA */ PAD_CFG_NC(GPP_C4),
/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
@ -145,7 +145,7 @@ static const struct pad_config gpio_table[] = {
/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),
/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),
/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),
@ -162,17 +162,17 @@ static const struct pad_config gpio_table[] = {
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
/* SATALED# */ PAD_CFG_NC(GPP_E8),
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
@ -185,8 +185,8 @@ static const struct pad_config gpio_table[] = {
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
@ -195,8 +195,8 @@ static const struct pad_config gpio_table[] = {
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@ -225,7 +225,7 @@ static const struct pad_config gpio_table[] = {
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
/* GPD7 */ PAD_CFG_NC(GPD7),
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),
/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),
/* LANPHYC */ PAD_CFG_NC(GPD11),

8
src/mainboard/intel/littleplains/irqroute.h
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@ -21,10 +21,10 @@
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
/*
* IR01h PCIe INT(ABCD) - PIRQ ABCD
* IR02h PCIe INT(ABCD) - PIRQ ABCD
* IR03h PCIe INT(ABCD) - PIRQ ABCD
* IR04h PCIe INT(ABCD) - PIRQ ABCD
* IR01h PCIe INT(ABCD) - PIRQ ABCD
* IR02h PCIe INT(ABCD) - PIRQ ABCD
* IR03h PCIe INT(ABCD) - PIRQ ABCD
* IR04h PCIe INT(ABCD) - PIRQ ABCD
* IR0Bh IQIA INT(ABCD) - PIRQ EFGH
* IR0Eh RAS INT(A) - PIRQ A
* IR13h SMBUS1 INT(A) - PIRQ B

8
src/mainboard/intel/mohonpeak/irqroute.h
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@ -21,10 +21,10 @@
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
/*
* IR01h PCIe INT(ABCD) - PIRQ ABCD
* IR02h PCIe INT(ABCD) - PIRQ ABCD
* IR03h PCIe INT(ABCD) - PIRQ ABCD
* IR04h PCIe INT(ABCD) - PIRQ ABCD
* IR01h PCIe INT(ABCD) - PIRQ ABCD
* IR02h PCIe INT(ABCD) - PIRQ ABCD
* IR03h PCIe INT(ABCD) - PIRQ ABCD
* IR04h PCIe INT(ABCD) - PIRQ ABCD
* IR0Bh IQIA INT(ABCD) - PIRQ EFGH
* IR0Eh RAS INT(A) - PIRQ A
* IR13h SMBUS1 INT(A) - PIRQ B

22
src/mainboard/intel/saddlebrook/gpio.h
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@ -239,17 +239,17 @@ static const struct pad_config gpio_table[] = {
/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* TBD */
/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),