drivers/ati/ragexl: Remove dead code
Is unused in the tree. Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22132 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
26a4b9d063
commit
cd7dfaf3b0
8 changed files with 0 additions and 3950 deletions
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@ -1,2 +0,0 @@
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config DRIVERS_ATI_RAGEXL
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bool
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@ -1 +0,0 @@
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ramstage-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c
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@ -1,407 +0,0 @@
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/*
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* ATI Frame Buffer Device Driver Core Definitions
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*/
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#define PLL_CRTC_DECODE 0
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#define EINVAL -1
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#if CONFIG_CONSOLE_BTEXT
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/*
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* Elements of the hardware specific atyfb_par structure
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*/
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struct crtc {
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u32 vxres;
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u32 vyres;
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u32 xoffset;
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u32 yoffset;
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u32 bpp;
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u32 h_tot_disp;
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u32 h_sync_strt_wid;
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u32 v_tot_disp;
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u32 v_sync_strt_wid;
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u32 off_pitch;
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u32 gen_cntl;
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u32 dp_pix_width; /* acceleration */
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u32 dp_chain_mask; /* acceleration */
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};
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#endif /* CONFIG_CONSOLE_BTEXT */
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#if 0
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struct pll_514 {
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u8 m;
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u8 n;
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};
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struct pll_18818
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{
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u32 program_bits;
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u32 locationAddr;
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u32 period_in_ps;
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u32 post_divider;
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};
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#endif
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struct pll_ct {
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u8 pll_ref_div;
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u8 pll_gen_cntl;
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u8 mclk_fb_div;
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u8 mclk_fb_mult; /* 2 or 4 */
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u8 sclk_fb_div;
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u8 pll_vclk_cntl;
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u8 vclk_post_div;
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u8 vclk_fb_div;
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u8 pll_ext_cntl;
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u8 spll_cntl2;
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u32 dsp_config; /* Mach64 GTB DSP */
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u32 dsp_on_off; /* Mach64 GTB DSP */
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u8 mclk_post_div_real;
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u8 xclk_post_div_real;
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u8 vclk_post_div_real;
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};
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union aty_pll {
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struct pll_ct ct;
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#if 0
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struct pll_514 ibm514;
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struct pll_18818 ics2595;
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#endif
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};
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/*
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* The hardware parameters for each card
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*/
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struct atyfb_par {
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#if CONFIG_CONSOLE_BTEXT
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struct crtc crtc;
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#endif
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union aty_pll pll;
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u32 accel_flags;
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};
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#if 0
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struct aty_cursor {
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int enable;
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int on;
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int vbl_cnt;
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int blink_rate;
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u32 offset;
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struct {
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u16 x, y;
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} pos, hot, size;
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u32 color[2];
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u8 bits[8][64];
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u8 mask[8][64];
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u8 *ram;
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struct timer_list *timer;
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};
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#endif
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struct fb_info_aty {
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#if CONFIG_CONSOLE_BTEXT
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#if PLL_CRTC_DECODE==1
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struct fb_info fb_info;
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#endif
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#endif
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#if 0
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struct fb_info_aty *next;
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unsigned long ati_regbase_phys;
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#endif
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u8 *ati_regbase;
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#if 0
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unsigned long frame_buffer_phys;
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#endif
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unsigned long frame_buffer;
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unsigned long clk_wr_offset;
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#if 0
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struct pci_mmap_map *mmap_map;
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struct aty_cursor *cursor;
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#endif
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struct aty_cmap_regs *aty_cmap_regs;
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#if 0
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struct { u8 red, green, blue, pad; } palette[256];
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#endif
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struct atyfb_par default_par;
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#if PLL_CRTC_DECODE==1
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struct atyfb_par current_par;
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#endif
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u32 features;
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u32 total_vram;
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u32 ref_clk_per;
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u32 pll_per;
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u32 mclk_per;
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u32 xclk_per;
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u8 bus_type;
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u8 ram_type;
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u8 mem_refresh_rate;
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#if 0
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struct aty_dac_ops *dac_ops;
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struct aty_pll_ops *pll_ops;
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struct display disp;
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struct display_switch dispsw;
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#endif
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#if 0
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union {
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#ifdef FBCON_HAS_CFB16
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u16 cfb16[16];
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#endif
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#ifdef FBCON_HAS_CFB24
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u32 cfb24[16];
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#endif
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#ifdef FBCON_HAS_CFB32
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u32 cfb32[16];
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#endif
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} fbcon_cmap;
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#endif
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u8 blitter_may_be_busy;
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#if 0
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#ifdef __sparc__
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u8 mmaped;
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int open;
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int vtconsole;
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int consolecnt;
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#endif
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#ifdef CONFIG_PMAC_PBOOK
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unsigned char *save_framebuffer;
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unsigned long save_pll[64];
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#endif
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#endif
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};
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/*
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* ATI Mach64 features
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*/
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#define M64_HAS(feature) ((info)->features & (M64F_##feature))
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#define M64F_RESET_3D 0x00000001
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#define M64F_MAGIC_FIFO 0x00000002
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#define M64F_GTB_DSP 0x00000004
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#define M64F_FIFO_24 0x00000008
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#define M64F_SDRAM_MAGIC_PLL 0x00000010
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#define M64F_MAGIC_POSTDIV 0x00000020
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#define M64F_INTEGRATED 0x00000040
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#define M64F_CT_BUS 0x00000080
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#define M64F_VT_BUS 0x00000100
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#define M64F_MOBIL_BUS 0x00000200
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#define M64F_GX 0x00000400
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#define M64F_CT 0x00000800
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#define M64F_VT 0x00001000
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#define M64F_GT 0x00002000
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#define M64F_MAGIC_VRAM_SIZE 0x00004000
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#define M64F_G3_PB_1_1 0x00008000
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#define M64F_G3_PB_1024x768 0x00010000
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#define M64F_EXTRA_BRIGHT 0x00020000
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#define M64F_LT_SLEEP 0x00040000
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#define M64F_XL_DLL 0x00080000
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#define M64F_MFB_TIMES_4 0x00100000
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/*
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* Register access
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*/
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static inline u32 aty_ld_le32(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef ATARI
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return in_le32((volatile u32 *)(info->ati_regbase+regindex));
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#else
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return read32 (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le32(int regindex, u32 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef ATARI
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out_le32 (info->ati_regbase+regindex, val);
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#else
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write32 (info->ati_regbase + regindex, val);
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#endif
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}
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static inline u16 aty_ld_le16(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#if defined(__mc68000__)
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return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));
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#else
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return read16 (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le16(int regindex, u16 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#if defined(__mc68000__)
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*((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);
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#else
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write16 (info->ati_regbase + regindex, val);
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#endif
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}
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static inline u8 aty_ld_8(int regindex,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef ATARI
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return in_8 (info->ati_regbase + regindex);
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#else
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return read8 (info->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_8(int regindex, u8 val,
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const struct fb_info_aty *info)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef ATARI
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out_8 (info->ati_regbase + regindex, val);
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#else
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write8 (info->ati_regbase + regindex, val);
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#endif
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}
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static inline u8 aty_ld_pll(int offset, const struct fb_info_aty *info)
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{
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u8 res;
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/* write addr byte */
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aty_st_8(CLOCK_CNTL + 1, (offset << 2), info);
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/* read the register value */
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res = aty_ld_8(CLOCK_CNTL + 2, info);
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return res;
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}
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/*
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* CT family only.
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*/
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static inline void aty_st_pll(int offset, u8 val,
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const struct fb_info_aty *info)
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{
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/* write addr byte */
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aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info);
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/* write the register value */
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aty_st_8(CLOCK_CNTL + 2, val, info);
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aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, info);
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}
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/*
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* DAC operations
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*/
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#if 0
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struct aty_dac_ops {
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int (*set_dac)(const struct fb_info_aty *info, const union aty_pll *pll,
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u32 bpp, u32 accel);
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};
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extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
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extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
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extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
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extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
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static struct aty_dac_ops aty_dac_ct; /* Integrated */
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#endif
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/*
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* Clock operations
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*/
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#if 0
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struct aty_pll_ops {
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int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp,
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union aty_pll *pll);
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#if 0
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u32 (*pll_to_var)(const struct fb_info_aty *info,
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const union aty_pll *pll);
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void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll);
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#endif
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};
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#endif
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#if 0
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extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
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extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
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extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
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extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
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extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
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extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
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#endif
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#if 0
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static struct aty_pll_ops aty_pll_ct; /* Integrated */
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static void aty_set_pll_ct(const struct fb_info_aty *info,
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const union aty_pll *pll);
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static void aty_calc_pll_ct(const struct fb_info_aty *info,
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struct pll_ct *pll);
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#endif
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#if 0
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/*
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* Hardware cursor support
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*/
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extern struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb);
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extern void atyfb_cursor(struct display *p, int mode, int x, int y);
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extern void aty_set_cursor_color(struct fb_info_aty *fb);
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extern void aty_set_cursor_shape(struct fb_info_aty *fb);
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extern int atyfb_set_font(struct display *d, int width, int height);
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#endif
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/*
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* Hardware acceleration
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*/
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static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info)
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{
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while ((aty_ld_le32(FIFO_STAT, info) & 0xffff) >
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((u32)(0x8000 >> entries)));
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}
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static inline void wait_for_idle(struct fb_info_aty *info)
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{
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wait_for_fifo(16, info);
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while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0);
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info->blitter_may_be_busy = 0;
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}
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#if 0
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extern void aty_reset_engine(const struct fb_info_aty *info);
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extern void aty_init_engine(const struct atyfb_par *par,
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struct fb_info_aty *info);
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extern void aty_rectfill(int dstx, int dsty, u32 width, u32 height,
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u32 color, struct fb_info_aty *info);
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/*
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* Text console acceleration
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*/
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extern const struct display_switch fbcon_aty8;
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extern const struct display_switch fbcon_aty16;
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extern const struct display_switch fbcon_aty24;
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extern const struct display_switch fbcon_aty32;
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#endif
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@ -1,344 +0,0 @@
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#ifndef _LINUX_FB_H
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#define _LINUX_FB_H
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#define u32 uint32_t
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#define u16 uint16_t
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#define u8 uint8_t
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#define s16 short
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/* Definitions of frame buffers */
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#define FB_MAJOR 29
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#define FB_MAX 32 /* sufficient for now */
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/* ioctls
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* 0x46 is 'F' */
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#define FBIOGET_VSCREENINFO 0x4600
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#define FBIOPUT_VSCREENINFO 0x4601
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#define FBIOGET_FSCREENINFO 0x4602
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#define FBIOGETCMAP 0x4604
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#define FBIOPUTCMAP 0x4605
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#define FBIOPAN_DISPLAY 0x4606
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/* 0x4607-0x460B are defined below */
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/* #define FBIOGET_MONITORSPEC 0x460C */
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/* #define FBIOPUT_MONITORSPEC 0x460D */
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/* #define FBIOSWITCH_MONIBIT 0x460E */
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#define FBIOGET_CON2FBMAP 0x460F
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#define FBIOPUT_CON2FBMAP 0x4610
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#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
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#define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank)
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#define FBIO_ALLOC 0x4613
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#define FBIO_FREE 0x4614
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#define FBIOGET_GLYPH 0x4615
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#define FBIOGET_HWCINFO 0x4616
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#define FBIOPUT_MODEINFO 0x4617
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#define FBIOGET_DISPINFO 0x4618
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#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
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#define FB_TYPE_PLANES 1 /* Non interleaved planes */
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#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
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#define FB_TYPE_TEXT 3 /* Text/attributes */
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#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
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#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
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#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
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#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
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#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
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#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
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#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
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#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
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#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
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#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
|
||||
#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
|
||||
#define FB_VISUAL_TRUECOLOR 2 /* True color */
|
||||
#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
|
||||
#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
|
||||
#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
|
||||
|
||||
#define FB_ACCEL_NONE 0 /* no hardware accelerator */
|
||||
#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
|
||||
#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
|
||||
#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
|
||||
#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
|
||||
#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
|
||||
#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
|
||||
#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
|
||||
#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
|
||||
#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
|
||||
#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
|
||||
#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
|
||||
#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
|
||||
#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
|
||||
#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
|
||||
#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
|
||||
#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
|
||||
#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
|
||||
#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
|
||||
#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
|
||||
#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
|
||||
#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
|
||||
#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
|
||||
#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
|
||||
#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
|
||||
#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
|
||||
#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
|
||||
#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
|
||||
#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
|
||||
#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
|
||||
#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
|
||||
#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
|
||||
#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
|
||||
#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
|
||||
#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
|
||||
#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
|
||||
|
||||
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
|
||||
|
||||
#if 0
|
||||
|
||||
struct fb_fix_screeninfo {
|
||||
char id[16]; /* identification string eg "TT Builtin" */
|
||||
unsigned long smem_start; /* Start of frame buffer mem */
|
||||
/* (physical address) */
|
||||
u32 smem_len; /* Length of frame buffer mem */
|
||||
u32 type; /* see FB_TYPE_* */
|
||||
u32 type_aux; /* Interleave for interleaved Planes */
|
||||
u32 visual; /* see FB_VISUAL_* */
|
||||
u16 xpanstep; /* zero if no hardware panning */
|
||||
u16 ypanstep; /* zero if no hardware panning */
|
||||
u16 ywrapstep; /* zero if no hardware ywrap */
|
||||
u32 line_length; /* length of a line in bytes */
|
||||
u8 *mmio_start; /* Start of Memory Mapped I/O */
|
||||
/* (physical address) */
|
||||
u32 mmio_len; /* Length of Memory Mapped I/O */
|
||||
u32 accel; /* Type of acceleration available */
|
||||
u16 reserved[3]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* Interpretation of offset for color fields: All offsets are from the right,
|
||||
* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
|
||||
* can use the offset as right argument to <<). A pixel afterwards is a bit
|
||||
* stream and is written to video memory as that unmodified. This implies
|
||||
* big-endian byte order if bits_per_pixel is greater than 8.
|
||||
*/
|
||||
struct fb_bitfield {
|
||||
u32 offset; /* beginning of bitfield */
|
||||
u32 length; /* length of bitfield */
|
||||
u32 msb_right; /* != 0 : Most significant bit is */
|
||||
/* right */
|
||||
};
|
||||
|
||||
#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
|
||||
|
||||
#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
|
||||
#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
|
||||
#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
|
||||
#define FB_ACTIVATE_MASK 15
|
||||
/* values */
|
||||
#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
|
||||
#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
|
||||
#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
|
||||
|
||||
#define FB_ACCELF_TEXT 1 /* text mode acceleration */
|
||||
|
||||
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
|
||||
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
|
||||
#define FB_SYNC_EXT 4 /* external sync */
|
||||
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
|
||||
#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
|
||||
/* vtotal = 144d/288n/576i => PAL */
|
||||
/* vtotal = 121d/242n/484i => NTSC */
|
||||
#define FB_SYNC_ON_GREEN 32 /* sync on green */
|
||||
|
||||
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
|
||||
#define FB_VMODE_INTERLACED 1 /* interlaced */
|
||||
#define FB_VMODE_DOUBLE 2 /* double scan */
|
||||
#define FB_VMODE_MASK 255
|
||||
|
||||
#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
|
||||
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
|
||||
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
|
||||
|
||||
struct fb_var_screeninfo {
|
||||
u32 xres; /* visible resolution */
|
||||
u32 yres;
|
||||
u32 xres_virtual; /* virtual resolution */
|
||||
u32 yres_virtual;
|
||||
u32 xoffset; /* offset from virtual to visible */
|
||||
u32 yoffset; /* resolution */
|
||||
|
||||
u32 bits_per_pixel; /* guess what */
|
||||
u32 grayscale; /* != 0 Graylevels instead of colors */
|
||||
|
||||
struct fb_bitfield red; /* bitfield in fb mem if true color, */
|
||||
struct fb_bitfield green; /* else only length is significant */
|
||||
struct fb_bitfield blue;
|
||||
struct fb_bitfield transp; /* transparency */
|
||||
|
||||
u32 nonstd; /* != 0 Non standard pixel format */
|
||||
|
||||
u32 activate; /* see FB_ACTIVATE_* */
|
||||
|
||||
u32 height; /* height of picture in mm */
|
||||
u32 width; /* width of picture in mm */
|
||||
|
||||
u32 accel_flags; /* acceleration flags (hints) */
|
||||
|
||||
/* Timing: All values in pixclocks, except pixclock (of course) */
|
||||
u32 pixclock; /* pixel clock in ps (pico seconds) */
|
||||
u32 left_margin; /* time from sync to picture */
|
||||
u32 right_margin; /* time from picture to sync */
|
||||
u32 upper_margin; /* time from sync to picture */
|
||||
u32 lower_margin;
|
||||
u32 hsync_len; /* length of horizontal sync */
|
||||
u32 vsync_len; /* length of vertical sync */
|
||||
u32 sync; /* see FB_SYNC_* */
|
||||
u32 vmode; /* see FB_VMODE_* */
|
||||
u32 reserved[6]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
struct fb_cmap {
|
||||
u32 start; /* First entry */
|
||||
u32 len; /* Number of entries */
|
||||
u16 *red; /* Red values */
|
||||
u16 *green;
|
||||
u16 *blue;
|
||||
u16 *transp; /* transparency, can be NULL */
|
||||
};
|
||||
|
||||
struct fb_con2fbmap {
|
||||
u32 console;
|
||||
u32 framebuffer;
|
||||
};
|
||||
|
||||
/* VESA Blanking Levels */
|
||||
#define VESA_NO_BLANKING 0
|
||||
#define VESA_VSYNC_SUSPEND 1
|
||||
#define VESA_HSYNC_SUSPEND 2
|
||||
#define VESA_POWERDOWN 3
|
||||
|
||||
struct fb_monspecs {
|
||||
u32 hfmin; /* hfreq lower limit (Hz) */
|
||||
u32 hfmax; /* hfreq upper limit (Hz) */
|
||||
u16 vfmin; /* vfreq lower limit (Hz) */
|
||||
u16 vfmax; /* vfreq upper limit (Hz) */
|
||||
unsigned dpms : 1; /* supports DPMS */
|
||||
};
|
||||
|
||||
#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */
|
||||
#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */
|
||||
#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */
|
||||
#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */
|
||||
#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */
|
||||
#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
|
||||
#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
|
||||
|
||||
struct fb_vblank {
|
||||
u32 flags; /* FB_VBLANK flags */
|
||||
u32 count; /* counter of retraces since boot */
|
||||
u32 vcount; /* current scanline position */
|
||||
u32 hcount; /* current scandot position */
|
||||
u32 reserved[4]; /* reserved for future compatibility */
|
||||
};
|
||||
|
||||
|
||||
#if 1
|
||||
|
||||
#define FBCMD_GET_CURRENTPAR 0xDEAD0005
|
||||
#define FBCMD_SET_CURRENTPAR 0xDEAD8005
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Hardware Cursor
|
||||
*/
|
||||
|
||||
#define FBIOGET_FCURSORINFO 0x4607
|
||||
#define FBIOGET_VCURSORINFO 0x4608
|
||||
#define FBIOPUT_VCURSORINFO 0x4609
|
||||
#define FBIOGET_CURSORSTATE 0x460A
|
||||
#define FBIOPUT_CURSORSTATE 0x460B
|
||||
|
||||
|
||||
struct fb_fix_cursorinfo {
|
||||
u16 crsr_width; /* width and height of the cursor in */
|
||||
u16 crsr_height; /* pixels (zero if no cursor) */
|
||||
u16 crsr_xsize; /* cursor size in display pixels */
|
||||
u16 crsr_ysize;
|
||||
u16 crsr_color1; /* colormap entry for cursor color1 */
|
||||
u16 crsr_color2; /* colormap entry for cursor color2 */
|
||||
};
|
||||
|
||||
struct fb_var_cursorinfo {
|
||||
u16 width;
|
||||
u16 height;
|
||||
u16 xspot;
|
||||
u16 yspot;
|
||||
u8 data[1]; /* field with [height][width] */
|
||||
};
|
||||
|
||||
struct fb_cursorstate {
|
||||
s16 xoffset;
|
||||
s16 yoffset;
|
||||
u16 mode;
|
||||
};
|
||||
|
||||
|
||||
struct fb_info {
|
||||
char modename[40]; /* default video mode */
|
||||
// kdev_t node;
|
||||
int flags;
|
||||
int open; /* Has this been open already ? */
|
||||
struct fb_var_screeninfo var; /* Current var */
|
||||
#if 0
|
||||
struct fb_fix_screeninfo fix; /* Current fix */
|
||||
#endif
|
||||
struct fb_monspecs monspecs; /* Current Monitor specs */
|
||||
struct fb_cmap cmap; /* Current cmap */
|
||||
// struct fb_ops *fbops;
|
||||
char *screen_base; /* Virtual address */
|
||||
struct display *disp; /* initial display variable */
|
||||
// struct vc_data *display_fg; /* Console visible on this display */
|
||||
char fontname[40]; /* default font name */
|
||||
#if 0
|
||||
devfs_handle_t devfs_handle; /* Devfs handle for new name */
|
||||
devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */
|
||||
int (*changevar)(int); /* tell console var has changed */
|
||||
int (*switch_con)(int, struct fb_info*);
|
||||
/* tell fb to switch consoles */
|
||||
int (*updatevar)(int, struct fb_info*);
|
||||
/* tell fb to update the vars */
|
||||
void (*blank)(int, struct fb_info*); /* tell fb to (un)blank the screen */
|
||||
/* arg = 0: unblank */
|
||||
/* arg > 0: VESA level (arg-1) */
|
||||
#endif
|
||||
void *pseudo_palette; /* Fake palette of 16 colors and
|
||||
the cursor's color for non
|
||||
palette mode */
|
||||
/* From here on everything is device dependent */
|
||||
void *par;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_FB_H */
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
/*
|
||||
* linux/drivers/video/fbcon.h -- Low level frame buffer based console driver
|
||||
*
|
||||
* Copyright (C) 1997 Geert Uytterhoeven
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef _VIDEO_FBCON_H
|
||||
#define _VIDEO_FBCON_H
|
||||
|
||||
struct display {
|
||||
/* Filled in by the frame buffer device */
|
||||
struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */
|
||||
/* are updated by fbcon.c */
|
||||
struct fb_cmap cmap; /* colormap */
|
||||
char *screen_base; /* pointer to top of virtual screen */
|
||||
/* (virtual address) */
|
||||
int visual;
|
||||
int type; /* see FB_TYPE_* */
|
||||
int type_aux; /* Interleave for interleaved Planes */
|
||||
u16 ypanstep; /* zero if no hardware ypan */
|
||||
u16 ywrapstep; /* zero if no hardware ywrap */
|
||||
u32 line_length; /* length of a line in bytes */
|
||||
u16 can_soft_blank; /* zero if no hardware blanking */
|
||||
u16 inverse; /* != 0 text black on white as default */
|
||||
|
||||
/* Filled in by the low-level console driver */
|
||||
|
||||
struct vc_data *conp; /* pointer to console data */
|
||||
int vrows; /* number of virtual rows */
|
||||
unsigned short cursor_x; /* current cursor position */
|
||||
unsigned short cursor_y;
|
||||
int fgcol; /* text colors */
|
||||
int bgcol;
|
||||
u32 next_line; /* offset to one line below */
|
||||
u32 next_plane; /* offset to next plane */
|
||||
u8 *fontdata; /* Font associated to this display */
|
||||
unsigned short _fontheightlog;
|
||||
unsigned short _fontwidthlog;
|
||||
unsigned short _fontheight;
|
||||
unsigned short _fontwidth;
|
||||
int userfont; /* != 0 if fontdata kmalloc()ed */
|
||||
u16 scrollmode; /* Scroll Method */
|
||||
short yscroll; /* Hardware scrolling */
|
||||
unsigned char fgshift, bgshift;
|
||||
unsigned short charmask; /* 0xff or 0x1ff */
|
||||
};
|
||||
|
||||
|
||||
#define fontheight(p) ((p)->_fontheight)
|
||||
#define fontheightlog(p) ((p)->_fontheightlog)
|
||||
|
||||
#ifdef FBCON_FONTWIDTH8_ONLY
|
||||
|
||||
/* fontwidth w is supported by dispsw */
|
||||
#define FONTWIDTH(w) (1 << ((8) - 1))
|
||||
/* fontwidths w1-w2 inclusive are supported by dispsw */
|
||||
#define FONTWIDTHRANGE(w1,w2) FONTWIDTH(8)
|
||||
|
||||
#define fontwidth(p) (8)
|
||||
#define fontwidthlog(p) (0)
|
||||
|
||||
#else
|
||||
|
||||
/* fontwidth w is supported by dispsw */
|
||||
#define FONTWIDTH(w) (1 << ((w) - 1))
|
||||
/* fontwidths w1-w2 inclusive are supported by dispsw */
|
||||
#define FONTWIDTHRANGE(w1,w2) (FONTWIDTH(w2+1) - FONTWIDTH(w1))
|
||||
|
||||
#define fontwidth(p) ((p)->_fontwidth)
|
||||
#define fontwidthlog(p) ((p)->_fontwidthlog)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Attribute Decoding
|
||||
*/
|
||||
|
||||
/* Color */
|
||||
#define attr_fgcol(p,s) \
|
||||
(((s) >> ((p)->fgshift)) & 0x0f)
|
||||
#define attr_bgcol(p,s) \
|
||||
(((s) >> ((p)->bgshift)) & 0x0f)
|
||||
#define attr_bgcol_ec(p,conp) \
|
||||
((conp) ? (((conp)->vc_video_erase_char >> ((p)->bgshift)) & 0x0f) : 0)
|
||||
|
||||
/* Monochrome */
|
||||
#define attr_bold(p,s) \
|
||||
((s) & 0x200)
|
||||
#define attr_reverse(p,s) \
|
||||
(((s) & 0x800) ^ ((p)->inverse ? 0x800 : 0))
|
||||
#define attr_underline(p,s) \
|
||||
((s) & 0x400)
|
||||
#define attr_blink(p,s) \
|
||||
((s) & 0x8000)
|
||||
|
||||
/*
|
||||
* Scroll Method
|
||||
*/
|
||||
|
||||
/* Internal flags */
|
||||
#define __SCROLL_YPAN 0x001
|
||||
#define __SCROLL_YWRAP 0x002
|
||||
#define __SCROLL_YMOVE 0x003
|
||||
#define __SCROLL_YREDRAW 0x004
|
||||
#define __SCROLL_YMASK 0x00f
|
||||
#define __SCROLL_YFIXED 0x010
|
||||
#define __SCROLL_YNOMOVE 0x020
|
||||
#define __SCROLL_YPANREDRAW 0x040
|
||||
#define __SCROLL_YNOPARTIAL 0x080
|
||||
|
||||
/* Only these should be used by the drivers */
|
||||
/* Which one should you use? If you have a fast card and slow bus,
|
||||
then probably just 0 to indicate fbcon should choose between
|
||||
YWRAP/YPAN+MOVE/YMOVE. On the other side, if you have a fast bus
|
||||
and even better if your card can do fonting (1->8/32bit painting),
|
||||
you should consider either SCROLL_YREDRAW (if your card is
|
||||
able to do neither YPAN/YWRAP), or SCROLL_YNOMOVE.
|
||||
The best is to test it with some real life scrolling (usually, not
|
||||
all lines on the screen are filled completely with non-space characters,
|
||||
and REDRAW performs much better on such lines, so don't cat a file
|
||||
with every line covering all screen columns, it would not be the right
|
||||
benchmark).
|
||||
*/
|
||||
#define SCROLL_YREDRAW (__SCROLL_YFIXED|__SCROLL_YREDRAW)
|
||||
#define SCROLL_YNOMOVE (__SCROLL_YNOMOVE|__SCROLL_YPANREDRAW)
|
||||
|
||||
/* SCROLL_YNOPARTIAL, used in combination with the above, is for video
|
||||
cards which can not handle using panning to scroll a portion of the
|
||||
screen without excessive flicker. Panning will only be used for
|
||||
whole screens.
|
||||
*/
|
||||
/* Namespace consistency */
|
||||
#define SCROLL_YNOPARTIAL __SCROLL_YNOPARTIAL
|
||||
|
||||
#endif /* _VIDEO_FBCON_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,370 +0,0 @@
|
|||
#define DEBUG_PLL 0
|
||||
#define PLL_CRTC_DECODE 0
|
||||
|
||||
/* FIXME: remove the FAIL definition */
|
||||
#if 0
|
||||
#define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0)
|
||||
#else
|
||||
#define FAIL(x)
|
||||
#endif
|
||||
|
||||
static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
struct pll_ct *pll);
|
||||
static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,
|
||||
struct pll_ct *pll);
|
||||
static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
u8 bpp, union aty_pll *pll);
|
||||
#if PLL_CRTC_DECODE==1
|
||||
static u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
|
||||
const union aty_pll *pll);
|
||||
#endif
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* PLL programming (Mach64 CT family)
|
||||
*/
|
||||
static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp,
|
||||
struct pll_ct *pll)
|
||||
{
|
||||
u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on;
|
||||
u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size;
|
||||
u32 memcntl, n, t_pfc, t_rp, t_ras, t_rcd, t_crd, t_rcc, t_lat;
|
||||
|
||||
#if DEBUG_PLL==1
|
||||
printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult);
|
||||
#endif
|
||||
|
||||
/* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */
|
||||
xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div *
|
||||
(u32)pll->vclk_post_div_real * 64) << 11;
|
||||
xclks_per_row /=
|
||||
(2 * (u32)pll->vclk_fb_div * (u32)pll->xclk_post_div_real * bpp);
|
||||
|
||||
if (xclks_per_row < (1<<11))
|
||||
FAIL("Dotclock too high");
|
||||
if (M64_HAS(FIFO_24)) {
|
||||
fifo_size = 24;
|
||||
dsp_loop_latency = 0;
|
||||
} else {
|
||||
fifo_size = 32;
|
||||
dsp_loop_latency = 2;
|
||||
}
|
||||
dsp_precision = 0;
|
||||
y = (xclks_per_row*fifo_size)>>11;
|
||||
while (y) {
|
||||
y >>= 1;
|
||||
dsp_precision++;
|
||||
}
|
||||
dsp_precision -= 5;
|
||||
|
||||
/* fifo_off<<6 */
|
||||
fifo_off = ((xclks_per_row*(fifo_size-1))>>5); // + (3<<6);
|
||||
|
||||
if (info->total_vram > 1*1024*1024) {
|
||||
switch (info->ram_type) {
|
||||
case WRAM:
|
||||
/* >1 MB WRAM */
|
||||
dsp_loop_latency += 9;
|
||||
n = 4;
|
||||
break;
|
||||
case SDRAM:
|
||||
case SGRAM:
|
||||
/* >1 MB SDRAM */
|
||||
dsp_loop_latency += 8;
|
||||
n = 2;
|
||||
break;
|
||||
default:
|
||||
/* >1 MB DRAM */
|
||||
dsp_loop_latency += 6;
|
||||
n = 3;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (info->ram_type >= SDRAM) {
|
||||
/* <2 MB SDRAM */
|
||||
dsp_loop_latency += 9;
|
||||
n = 2;
|
||||
} else {
|
||||
/* <2 MB DRAM */
|
||||
dsp_loop_latency += 8;
|
||||
n = 3;
|
||||
}
|
||||
}
|
||||
|
||||
memcntl = aty_ld_le32(MEM_CNTL, info);
|
||||
t_rcd = ((memcntl >> 10) & 0x03) + 1;
|
||||
t_crd = ((memcntl >> 12) & 0x01);
|
||||
t_rp = ((memcntl >> 8) & 0x03) + 1;
|
||||
t_ras = ((memcntl >> 16) & 0x07) + 1;
|
||||
t_lat = (memcntl >> 4) & 0x03;
|
||||
|
||||
t_pfc = t_rp + t_rcd + t_crd;
|
||||
|
||||
t_rcc = max(t_rp + t_ras, t_pfc + n);
|
||||
|
||||
/* fifo_on<<6 */
|
||||
fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6;
|
||||
|
||||
dsp_xclks_per_row = xclks_per_row>>dsp_precision;
|
||||
dsp_on = fifo_on>>dsp_precision;
|
||||
dsp_off = fifo_off>>dsp_precision;
|
||||
|
||||
pll->dsp_config = (dsp_xclks_per_row & 0x3fff) |
|
||||
((dsp_loop_latency & 0xf)<<16) |
|
||||
((dsp_precision & 7)<<20);
|
||||
pll->dsp_on_off = (dsp_off & 0x7ff) | ((dsp_on & 0x7ff)<<16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
struct pll_ct *pll)
|
||||
{
|
||||
#if DEBUG_PLL==1
|
||||
int pllmclk, pllsclk;
|
||||
#endif
|
||||
u32 q;
|
||||
|
||||
pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;
|
||||
|
||||
/* FIXME: use the VTB/GTB /3 post divider if it's better suited */
|
||||
|
||||
/* actually 8*q */
|
||||
q = info->ref_clk_per*pll->pll_ref_div*4/info->mclk_per;
|
||||
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("mclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->mclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->mclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->mclk_post_div_real = 2;
|
||||
else
|
||||
pll->mclk_post_div_real = 1;
|
||||
pll->sclk_fb_div = q*pll->mclk_post_div_real/8;
|
||||
|
||||
#if DEBUG_PLL==1
|
||||
pllsclk = (1000000 * 2 * pll->sclk_fb_div) /
|
||||
(info->ref_clk_per * pll->pll_ref_div);
|
||||
|
||||
printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n",
|
||||
pllsclk, pllsclk / pll->mclk_post_div_real);
|
||||
#endif
|
||||
|
||||
pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2;
|
||||
|
||||
/* actually 8*q */
|
||||
q = info->ref_clk_per * pll->pll_ref_div * 8 /
|
||||
(pll->mclk_fb_mult * info->xclk_per);
|
||||
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("mclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->xclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->xclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->xclk_post_div_real = 2;
|
||||
else
|
||||
pll->xclk_post_div_real = 1;
|
||||
pll->mclk_fb_div = q*pll->xclk_post_div_real/8;
|
||||
|
||||
#if DEBUG_PLL==1
|
||||
pllmclk = (1000000 * pll->mclk_fb_mult * pll->mclk_fb_div) /
|
||||
(info->ref_clk_per * pll->pll_ref_div);
|
||||
printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n",
|
||||
pllmclk, pllmclk / pll->xclk_post_div_real);
|
||||
#endif
|
||||
|
||||
/* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
|
||||
q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */
|
||||
if (q < 16*8 || q > 255*8)
|
||||
FAIL("vclk out of range\n");
|
||||
else if (q < 32*8)
|
||||
pll->vclk_post_div_real = 8;
|
||||
else if (q < 64*8)
|
||||
pll->vclk_post_div_real = 4;
|
||||
else if (q < 128*8)
|
||||
pll->vclk_post_div_real = 2;
|
||||
else
|
||||
pll->vclk_post_div_real = 1;
|
||||
pll->vclk_fb_div = q*pll->vclk_post_div_real/8;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll)
|
||||
{
|
||||
u8 xpostdiv = 0;
|
||||
u8 mpostdiv = 0;
|
||||
u8 vpostdiv = 0;
|
||||
|
||||
if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM))
|
||||
pll->pll_gen_cntl = 0x64; /* mclk = sclk */
|
||||
else
|
||||
pll->pll_gen_cntl = 0xe4; /* mclk = sclk */
|
||||
|
||||
switch (pll->mclk_post_div_real) {
|
||||
case 1:
|
||||
mpostdiv = 0;
|
||||
break;
|
||||
case 2:
|
||||
mpostdiv = 1;
|
||||
break;
|
||||
case 4:
|
||||
mpostdiv = 2;
|
||||
break;
|
||||
case 8:
|
||||
mpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */
|
||||
|
||||
switch (pll->xclk_post_div_real) {
|
||||
case 1:
|
||||
xpostdiv = 0;
|
||||
break;
|
||||
case 2:
|
||||
xpostdiv = 1;
|
||||
break;
|
||||
case 3:
|
||||
xpostdiv = 4;
|
||||
break;
|
||||
case 4:
|
||||
xpostdiv = 2;
|
||||
break;
|
||||
case 8:
|
||||
xpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
if (M64_HAS(MAGIC_POSTDIV))
|
||||
pll->pll_ext_cntl = 0;
|
||||
else
|
||||
pll->pll_ext_cntl = xpostdiv; /* xclk == pllmclk / xpostdiv */
|
||||
|
||||
if (pll->mclk_fb_mult == 4)
|
||||
pll->pll_ext_cntl |= 0x08;
|
||||
|
||||
switch (pll->vclk_post_div_real) {
|
||||
case 2:
|
||||
vpostdiv = 1;
|
||||
break;
|
||||
case 3:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 1:
|
||||
vpostdiv = 0;
|
||||
break;
|
||||
case 6:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 4:
|
||||
vpostdiv = 2;
|
||||
break;
|
||||
case 12:
|
||||
pll->pll_ext_cntl |= 0x10;
|
||||
case 8:
|
||||
vpostdiv = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
|
||||
pll->vclk_post_div = vpostdiv;
|
||||
}
|
||||
|
||||
int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
|
||||
u8 bpp, union aty_pll *pll)
|
||||
{
|
||||
int err;
|
||||
if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
|
||||
return err;
|
||||
if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
|
||||
return err;
|
||||
aty_calc_pll_ct(info, &pll->ct);
|
||||
return 0;
|
||||
}
|
||||
#if CONFIG_CONSOLE_BTEXT
|
||||
#if PLL_CRTC_DECODE==1
|
||||
u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
|
||||
const union aty_pll *pll)
|
||||
{
|
||||
u32 ref_clk_per = info->ref_clk_per;
|
||||
u8 pll_ref_div = pll->ct.pll_ref_div;
|
||||
u8 vclk_fb_div = pll->ct.vclk_fb_div;
|
||||
u8 vclk_post_div = pll->ct.vclk_post_div_real;
|
||||
|
||||
return ref_clk_per*pll_ref_div*vclk_post_div/vclk_fb_div/2;
|
||||
}
|
||||
#endif
|
||||
void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll)
|
||||
{
|
||||
#if DEBUG_PLL==1
|
||||
printk(BIOS_DEBUG, "aty_set_pll_ct: about to program:\n"
|
||||
"refdiv=%d, extcntl=0x%02x, mfbdiv=%d\n"
|
||||
"spllcntl2=0x%02x, sfbdiv=%d, gencntl=0x%02x\n"
|
||||
"vclkcntl=0x%02x, vpostdiv=0x%02x, vfbdiv=%d\n"
|
||||
"clocksel=%d\n",
|
||||
pll->ct.pll_ref_div, pll->ct.pll_ext_cntl,
|
||||
pll->ct.mclk_fb_div, pll->ct.spll_cntl2,
|
||||
pll->ct.sclk_fb_div, pll->ct.pll_gen_cntl,
|
||||
pll->ct.pll_vclk_cntl, pll->ct.vclk_post_div,
|
||||
pll->ct.vclk_fb_div, aty_ld_le32(CLOCK_CNTL, info) & 0x03);
|
||||
#endif
|
||||
|
||||
aty_st_pll(PLL_REF_DIV, pll->ct.pll_ref_div, info);
|
||||
|
||||
aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info);
|
||||
aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK
|
||||
|
||||
aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info);
|
||||
aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK
|
||||
|
||||
aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info);
|
||||
|
||||
aty_st_pll(EXT_VPLL_CNTL, 0, info);
|
||||
aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info);
|
||||
aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info);
|
||||
aty_st_pll(VCLK0_FB_DIV, pll->ct.vclk_fb_div, info);
|
||||
|
||||
if (M64_HAS(GTB_DSP)) {
|
||||
u8 dll_cntl;
|
||||
|
||||
if (M64_HAS(XL_DLL))
|
||||
dll_cntl = 0x80;
|
||||
else if (info->ram_type >= SDRAM)
|
||||
dll_cntl = 0xa6;
|
||||
else
|
||||
dll_cntl = 0xa0;
|
||||
aty_st_pll(DLL_CNTL, dll_cntl, info);
|
||||
aty_st_pll(VFC_CNTL, 0x1b, info);
|
||||
aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, info);
|
||||
aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, info);
|
||||
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl, info);
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl | 0x40, info);
|
||||
mdelay(10);
|
||||
aty_st_pll(DLL_CNTL, dll_cntl & ~0x40, info);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
static int dummy(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static struct aty_dac_ops aty_dac_ct = {
|
||||
set_dac: (void *)dummy,
|
||||
};
|
||||
|
||||
static struct aty_pll_ops aty_pll_ct = {
|
||||
var_to_pll: aty_var_to_pll_ct,
|
||||
#if 0
|
||||
pll_to_var: aty_pll_ct_to_var,
|
||||
set_pll: aty_set_pll_ct,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_CONSOLE_BTEXT */
|
||||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue