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soc/amd/common: Refactor ACPIMMIO posted writes 

Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-06-26 10:22:24 +03:00 committed by Felix Held
parent 6a8c96f169
commit cd8d0e6ce6
3 changed files with 6 additions and 8 deletions
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6
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -387,12 +387,6 @@ static inline void gpio_write32(uint8_t gpio_num, uint32_t value)
write32(gpio_ctrl_ptr(gpio_num), value);
}
static inline void gpio_write32_rb(uint8_t gpio_num, uint32_t value)
{
write32(gpio_ctrl_ptr(gpio_num), value);
read32(gpio_ctrl_ptr(gpio_num));
}
/* GPIO bank 0 */
static inline uint8_t gpio0_read8(uint8_t reg)
{

4
src/soc/amd/picasso/i2c.c
View File

@ -169,9 +169,11 @@ static void save_i2c_pin_registers(uint8_t gpio,
static void restore_i2c_pin_registers(uint8_t gpio,
struct soc_amd_i2c_save *save_table)
{
/* Write and flush posted writes. */
iomux_write8(gpio, save_table->mux_value);
iomux_read8(gpio);
gpio_write32_rb(gpio, save_table->control_value);
gpio_write32(gpio, save_table->control_value);
gpio_read32(gpio);
}
/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */

4
src/soc/amd/stoneyridge/i2c.c
View File

@ -144,9 +144,11 @@ static void save_i2c_pin_registers(uint8_t gpio,
static void restore_i2c_pin_registers(uint8_t gpio,
struct soc_amd_i2c_save *save_table)
{
/* Write and flush posted writes. */
iomux_write8(gpio, save_table->mux_value);
iomux_read8(gpio);
gpio_write32_rb(gpio, save_table->control_value);
gpio_write32(gpio, save_table->control_value);
gpio_read32(gpio);
}
/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */