diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
index b1d04cccd2..cd9f12ee11 100644
--- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
+++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
@@ -15,7 +15,7 @@
 #define  TSN_MAC_PHYAD(pa)		(pa << 21)	/* Physical Layer Address */
 #define  TSN_MAC_REGAD(rda)		(rda << 16)	/* Register/Device Address */
 #define  TSN_MAC_CLK_TRAIL_4		(4 << 12)	/* 4 Trailing Clocks */
-#define  TSN_MAC_CSR_CLK_DIV_62		(1 << 8)	/* 0001: CSR=100-150 MHz; CSR/62 */
+#define  TSN_MAC_CSR_CLK_DIV_102	(1 << 10)	/* 0100: CSR=150-250 MHz; CSR/102 */
 #define  TSN_MAC_OP_CMD_WRITE		(1 << 2)	/* GMII Operation Command Write */
 #define  TSN_MAC_OP_CMD_READ		(3 << 2)	/* GMII Operation Command Read */
 #define  TSN_MAC_GMII_BUSY		(1 << 0)	/* GMII Busy bit */
diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c
index 3e08897c5c..2a1468c4f2 100644
--- a/src/soc/intel/elkhartlake/tsn_gbe.c
+++ b/src/soc/intel/elkhartlake/tsn_gbe.c
@@ -52,7 +52,7 @@ uint16_t tsn_mdio_read(void *base, uint8_t phy_adr, uint8_t reg_adr)
 
 	clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK,
 			TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr)
-			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62
+			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102
 			| TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY);
 
 	/* Wait for MDIO frame transfer to complete before reading MDIO DATA register */
@@ -75,7 +75,7 @@ void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data)
 	write16(base + TSN_MAC_MDIO_DATA, data);
 	clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK,
 			TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr)
-			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_62
+			| TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102
 			| TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY);
 
 	/* Wait for MDIO frame transfer to complete before do next */