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soc/intel/cache_as_ram.S: Add macro to detect bootguard nem 

Change-Id: I3867fce29d23b647fad9845b9a5c08bb949fa354
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-06-23 10:48:28 +02:00 committed by Patrick Georgi
parent 0007fa96a1
commit cd96fed5dc
1 changed files with 14 additions and 6 deletions
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20
src/soc/intel/common/block/cpu/car/cache_as_ram.S
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@ -59,6 +59,18 @@
rep stosl
.endm
/*
* macro: is_bootguard_nem
* Checks if the Bootguard ACM has enabled non eviction mode
* Clobbers %eax, %ecx, %edx
* Returns %eax and sets/unsets zero flag
*/
.macro is_bootguard_nem
movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
rdmsr
andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
.endm
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
@ -66,9 +78,7 @@ bootblock_pre_c_entry:
/* Bootguard sets up its own CAR and needs separate handling */
check_boot_guard:
movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
rdmsr
andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
is_bootguard_nem
jz no_bootguard
/* Disable PBE timer */
@ -204,9 +214,7 @@ setup_car_mtrr:
#endif
post_code(0x25)
movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
rdmsr
andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
is_bootguard_nem
jz no_bootguard_car_continue
clear_car