soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE

* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE

Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5
Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-on: https://review.coreboot.org/c/26928
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vanessa Eusebio 2018-06-06 13:12:53 -07:00 committed by Patrick Georgi
parent 2dfa53f80e
commit cd97982e2e
1 changed files with 1 additions and 0 deletions

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@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select UDELAY_TSC select UDELAY_TSC
select UDK_2015_BINDING select UDK_2015_BINDING
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
config FSP_T_ADDR config FSP_T_ADDR
hex "Intel FSP-T (temp ram init) binary location" hex "Intel FSP-T (temp ram init) binary location"