soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_SYNC_MFENCE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select UDELAY_TSC
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select UDK_2015_BINDING
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select UDK_2015_BINDING
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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config FSP_T_ADDR
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config FSP_T_ADDR
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hex "Intel FSP-T (temp ram init) binary location"
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hex "Intel FSP-T (temp ram init) binary location"
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