mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GB
Samsung K4E6E304EC-EGCG-4GB # 1011 BUG=b:179455694 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass stress test under run-in. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978 Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,7 +16,7 @@ static const struct mt8173_sdram_params sdram_configs[] = {
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#include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */
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#include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */
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#include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1001 */
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#include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1001 */
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#include "sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc" /* ram_code = 1010 */
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#include "sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc" /* ram_code = 1010 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
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#include "sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc" /* ram_code = 1011 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
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#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
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@ -0,0 +1,116 @@
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{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xb,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 2, 1, 1, 4, 3, 0, 0, 0, 0, 0},
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[CHANNEL_B] = { 0, 0, 0, 0, 0, 4, 3, 2, 3, 4}
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},
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.ca_train_center = {
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[CHANNEL_A] = 0,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 4, 5, 3}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 29, 64},
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{ 29, 64}
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},
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[CHANNEL_B] = {
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{ 29, 72},
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{ 29, 72}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0xd0b0909,
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[CHANNEL_B] = 0xa090809
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x0020202,
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0x4030102,
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0x2040100,
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0x1020102,
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0x1050100,
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0x5040403,
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0x5050706,
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0x0030304
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},
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[CHANNEL_B] = {
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0x2020202,
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0x5020200,
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0x1010200,
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0x2000100,
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0x1030100,
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0x2040202,
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0x2040503,
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0x0010103
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c1,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0xa053a057,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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